Okay, this is AFAIK, based on some classes I took in college.

This is assuming you want to know about an ordinary Symetric Multiprocessing system. cc-numa, numa, and other whacky ways to run things are not included.

> Do they share RAM on different clock timings?

No, they share the ram based on who needs it for each individual cycle, by arbitration.

> Do they share only certain parts of RAM, or all of it?

All of it is shared.

> Is there some multi-port RAM involved?

No. Just an arbiter on the system bus. The PIII bus is designed to have multiple processors on it and they self-arbitrate. The Athlon/Alpha bus is designed to be point-to-point, where the CPU talks directly to the chipset and such. In either case, there's no need for multi-port RAM or cycle stealing.

Also remember that memory is too slow for modern CPUs. So cycle stealing would be a Bad Thing.

The headache comes in when you consider the cache and the issues of cache coherence between processors. The processor cache is not shared between processors, so that has to be kept up to date with the rest of the system, and if another processor access what's in your cache, you have to mark that data as invalid.

> Which CPU talks to peripherals, and who decides?

All of the CPUs talk to peripherals. The OS handles the decision with semaphores and mutexes and stuff.

Of course, the problem is that the processors guarantee that semaphores work via the mutex instructions. Which rasies a lot of hairy problems for the 6502, as far as synchronization. In order to adequately syncronize processes and not have things stomping on each other, you need to make sure that you can create semaphores.

Nontheless, it isn't impossible to do a multi-6502 system. It would just be a wacky project.

Incidentally, I wonder how small a 65816 could be made, in terms of the die size. I'm picturing a connection-machine style supercomputer for 3D graphics. With one processor and a few megs of RAM for each processor, you could do some interesting things, especially if you could fit a lot of processors on a single chip, including RAM and perepherals.

What you've said is the "party-line" that's been preached in schools for years, but with relatively slow processors and relatively fast memory (e.g. the 15 ns 64Kx8 cache memories lying in the closet on a broken or no-longer fashionable motherboard) it's possible to share the whole thing with little complicating factors, except where the programming is concerned. IF you dedicate a region of memory, and it doesn't have to be large, for use as semaphore registers, and IF you've got a task or two that can be coordinated by using multiple processors sharing a memory pool and sharing other hardware features, multiple processors are quite easy. If you fiddle with the clock duty cycle so the phase-2 is short enough to allow several processors to access it during a cycle, then you could probly run 10-20 processors on a single RAM device. All you'd have to do is generate a clock with a common phase-1 and several different phase-2's. It's easy with a johnson counter, (see CMOS 4017 and the like) as it gives you several mutually exclusive positive-going pulses out and a symmetrical divide-by-5 output as well that are useful for timing shared access while keeping slow peripheral chips synchronized.

Uli