floobydust wrote:
First, Welcome and thanks for posting info on your SBC plans. Not sure where you are in Germany, but I used to travel there extensively during the 90's and 2000's... and lived for a couple years in Reutlingen.
Thanks for the welcome. I live in Hattingen, near Bochum, Ruhrgebiet.
floobydust wrote:
- Power supply: as you're using an input diode for blocking reverse voltage, why not replace it with a full-wave bridge? This would allow any polarity on the input and always power the SBC.
It's only a insurance against reverse polarity. I have always an 9v or 12V dc power supply with the right plug polarity availble. So no need for a full bridge design.
floobydust wrote:
- 16V8 PLD: I would recommend using the 22V10 instead. It has more lines and would be a better glue chip. I used one in my C02 Pocket SBC and my Github page has the schematic and code for it.
I have a couple of 22V10 and 18V8 here. So i can change this any time. But this is my first cpld aproach. I like
KISS.
floobydust wrote:
- R65C51: This is a very old design, really for modems. Note that the older Rockwell parts are not easily found, much less in the higher 4MHz versions. Also note that the recent WDC W65C02 part has a defect with the transmit bit in the status register - there's a long post on the forum here that covers that in gory detail. Using a newer UART/DUART would be a better choice. I (and several others) have switched to NXP chips, mostly the SC28L92 DUART which has two serial ports and a counter/timer.
SC28L92 is only avaible in non DIL packages...
i had a some R65xxx already in stock, so i would like to use them.
floobydust wrote:
Also, when coding the PLD, it's best to keep the chip select lines decoded only using the address lines from the CPU. You do need to qualify the Write (and Read) signals for memory and other device to Ph2 clock. Using the 22V10, you can have qualified Read and Write signals, RAM and ROM select lines and 5- I/O selects that are 32-bytes wide.
i got the idea from Garth 6502 primer.
http://wilsonminesco.com/6502primer/addr_decoding.htmlAll the /CS lines there are qualified with Phi2. I simply put this in CPLD code.
floobydust wrote:
...use a DS1813 as an NMI trigger with a momentary switch to trigger a Panic routine.
thats a nice idea.
floobydust wrote:
If you use a larger RAM chip, you can easily change your memory map (just recode the PLD) to get more contiguous RAM memory if needed. Also, where you decode your I/O can make a difference in how you can manage your memory mapping. I always use Page $FE for hardware I/O. This allows a more flexible memory map for contiguous memory.
In the first designs my io page was located at dxxx, like the c64. But i switched to the actual layout, because i have 128MB Flash (SST39SF010SA), which i want to use as ROM. Than i can have 8 different pages for Kernel ROM. And i have another 12KB addressspace for some kind of interpreter or programming.
floobydust wrote:
FInally, best of luck on getting your SBC up and running... there's lots of expertise out here... just ask if you have any questions... and have FUN!
I will do that. Thanks for your feedback.
_________________
don't count on me, i'm engineer (Animotion)
my arduino pages:
http://rcarduino.de