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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I recall reading through plasmo's testing. It was quite interesting.

For RF65816SBC, because there are two 8ns buffers around the SRAM, the minimum typical time would be around 30 ns. So, I am guessing this circuit will for sure not work over 30 MHz even though the processor may be able to go faster. I was more interested in how low a frequency it could be made to operate at. The clock generator has a minimum frequency of 3.75 MHz. I have set it up to try and use the best possible range. The maximum frequency of the setup is 26 MHz. Frequency steps are 51062.5 Hz. Note the chip is capable of much higher frequencies but since the circuit for sure won’t work at 30 MHz I picked 26 as the top. Legal multiplier values to be loaded into the PA port are then 37 to 255.

It was only a gate away, and a little bit of thought, from the FPGA module being able to become a bus master and access the RAM. The data direction through the data buffer needed to be inverted when the FPGA is the master, this required a ‘xor’ gate. With the one left over pin, it was used to drive the BE signal. To access the bus BE is driven low during the low portion of the PH2 clock and gates the clock off allowing the FPGA access. In theory the FPGA can master the bus now.

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http://www.finitron.ca

I added an alternate low frequency clock generator based around the 4046 chip. The base frequency of the generator is derived from the horizontal sync pulse divided by two, or 15625 Hz. The circuit should max out at about 4MHz.

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http://www.finitron.ca

By using the CPU at 3.3V I was able to make most of the design for 3.3V and eliminated a data buffer and associated logic. I also shifted the RAM modules over a chip select so they are at 4x, 8x and Cx. The boot in the FPGA now occupies 0x and does not need swapping with RAM. There is a 512kB RAM area on the FPGA module. I managed to free up a couple of pins on the module, so made the VGA eight-bit RGB332. I moved the 6522 select out to a ‘521 chip, freeing a pin on the FPGA module. The chip select logic is no longer done by the FPGA which was a timing concern. I/O is at the end of the first 4MB memory area. The last 12MB is all RAM. I have updated the schematics yet again. They are posted in my Github account.

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http://www.finitron.ca