This kept me busy today, doubt I'll ever build it, but coming up with schematics was fun. It started out as schematics for a RAM board and ended up containing the whole computer.

The SBC uses a programmable clock generator that can generate frequencies between 150kHz and 40MHz in 150kHz steps.

I have the divider value connected to a 6522 port A. If the direction of the port is switched to output what value appears on the pins?

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http://www.finitron.ca

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Interesting. Why do the SRAM's each have two A18 pins?

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

There's this: https://www.mouser.co.uk/datasheet/2/10 ... 540334.pdf

2Mx8 or 1Mx16 configurable 5V SRAM, but it's a bit slower at 45ns. Probably be ok with a 65C816 if you don't want to run it absolutely flat out.

Interesting schematic to look at!

I'm guessing the dual DS1813 arrangement is to debounce NMI? Is that why the one for RST is delayed, so that NMI is not triggered on power up?

You might want to OR VDA and VPA and use the result for the second chip select on your VIA, to ensure spurious reads are not generated that could mess with the internal function of the chip. Or even just VDA by itself (EDIT: nevermind, the VIA is only accessed by the A7)

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BB816 Computer YouTube series

This. (Emphasis added.)

It's easy to avoid the necessity for including an OR gate. Just choose the (2) configuration shown in the lower half of this diagram.

Or, feed VDA directly to the I/O devices (if, like most 65xx peripherals, they have an extra Chip Select input).

I elaborate on these three approaches here.
-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Reset has not been worked out yet. Since the FPGA is supplying a read / write strobe and the boot ROM not much can be done until it has loaded. It may be necessary to reset the circuit again after the FPGA loaded. The DS1813 idea borrowed from the POC SBC. I think to generate an NMI on power fail faster than a reset.

With SRAM density requiring more address lines, an idea would be to have an SRAM module that could plug into one of the older DRAM sockets. It may then replace DRAM in an older system. It would require a latch for the higher order address lines but its fewer pins to manage.

Yeah, VDA, VPA are used to qualify accesses and would be decoded in the FPGA as part of the 6522's circuit select.

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I just realized from your response that his design is using your memory modules, and went and read your datasheet. It is much clearer now.

If I am read and understanding the diagram right, this SBC design features a 65C816 CPU and a '573 latch for capturing the bank byte. The 24 address lines from CPU and the latch are routed through three '245 bus transceivers. The upper two address lines, A22 and A23, feed into a pair of '139 2-to-4 decoders that feeds the enables (WE0/1 and OE0/1) for the three memory modules, while the next three address lines, A19-A21, are routed to a '138 3-to-8 decoder to feed the chip enables on the memory modules. The data lines also have a '245 bus transceiver between the CPU and the memory modules. I assume the '245 transceivers are present to allow tri-stating. The '244 appears to be taking the RWB signal from the CPU an sending it on to the enables for the '139 2-to-4 encoders that enable the memory modules, but one of those has an inverter on it - I think this means that one '139 sends logical true to OE0/1 on the memory modules, or the other sends signals logical true to WE0/1.

The FPGA is connected to the data lines, again with a '245 bus transceiver between the FPGA and the data bus. About half the address lines appear to be connected, too. The FGPA is connected to the VDIP2-32 via four-line serial. It also looks to generate 6-bit RGB color (2 bits per color channel) and HSYNC and VSYNC signals for VGA output, and an audio signal that goes to an LM386 op-amp.

It appears to be a mixed voltage design, with most chips being fed 5V, 3.3V for the LVC family parts, and 12V for the LM386 op-amp.

That sums up the design well.

The '245 transceivers on the address bus are dual purpose and always enabled (not tri-stated) They are used to buffer the address lines since there are over 24 chips to drive onto RAM modules. At the same time they are used to level shift the signals to something the FPGA can digest.

One thing missing yet is accommodation for mass storage. Something could be interfaced to the second port of the 6522. The FPGA has analog inputs that are not being used. Perhaps they could be used for audio input. It may also be possible to use the UCB port of the keyboard / mouse.

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Just realized there is a flaw in the design. In order to support a VGA port I axed some of the address lines going to the FPGA. So, unless the boot program is 16 bytes or less, there is no way to boot the system. It looks like it needs a ROM yet or other device.

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My serial bootstrap is 18 bytes but the serial port is located in high memory. So if the serial port is located in zero page, the bootstrap code can fit in 16 bytes.
Bill

Thanks for reading through my description and explaining further.

I repurposed A14 going to the FPGA to be used as a ROM select and added a ROM to the design. It will be somewhat tricky to boot as RAM at bank zero will be disabled until a switch is set in the FPGA to allow the ROM to exist in bank zero where it is needed for boot. I think the ROM will need to be copied twice, but it can be done.
I/O blocks are now 32kB in size.

I also added an audio input circuit.


That is very tempting to do. Serial boot through a USB port should be possible then, but it means swapping the keyboard or mouse around.

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The ROM is out now. I managed to the use FPGA module by noting the bank address is on the data pins when ph2 is low. Using a couple of unused ‘and’ gates to control the ‘245 buffer to the FPGA allows it to see the bank address. That freed up the address pins used for A16 to A23, which were promptly used for lower address bits. So, the FPGA sees the entire 24-bit address now. I also freed up a pin on the FPGA by moving VDA to the 6522, so it is setup like Jeff suggested.

If the CPU is run at 3.3V and it has enough drive strength to drive about 26 CMOS chips, 3 RAM modules, then the address and data buffers can be removed from the design reducing the chip count by five.
I was reviewing the ‘265 micro-controller. If that chip is used instead of the ‘816 then the chip count is reduced further, by at least one, for the address latch.

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