In Daryl's SBC 2.5, I noticed he uses PHI2-O as CLK2. Which, IIRC, is a slightly delayed equivalent PHI2 signal (system clock).

I've read that we shouldn't use PHI2-O in new designs or any design that uses the CMOS version.

Now...my question then becomes...is there a reason to use a "slightly delayed" PHI2 at all in a new design with a 65C02?

Assuming 1 - 4 MHz design and fast SRAM...is there a need?

If so, I'm assuming something like a couple of flip-flops would usually suffice? Not to mention it squares out the signal a little more any way.

Thanks!

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Cat; the other white meat.

I have memorized the following:

1. Old schematics using PHI2O can be used with no alteration if one is using old stuff (NMOS and CMOS).
2. If one is going to use a WDC65C02 things might work (low clock speed, slow RAM, ROM, I/O) without any issues.
3. Using PHI2O on a (new) WDC 65C02 is not recommended (that is explicitly said in the data sheet). Together with fast RAM (< 70ns) there is a good chance to run into spurious errors. Use PHI2(in) = the output of your can oscillator instead.

Of course: all this assumes that the used schematics itself are free of errors.

When using a WDC65C02 it is better to use PHI2(in) (signal at DIL pin 37) instead of PHI2O (DIL pin 39) even when slow peripherals are used.

When using a WDC65C02 careful check the usage of the RDY signal. This is now an I/O signal (on all other 6502 it is input only).

If you wish to go beyond 10 MHz reading and understanding Generating Wait-States with Clock Trickery is recommended.


Regards

My original SBC-1 and SBC-2 used non-WDC 65C02 chips and that is why I used PHI2O. I agree that new WDC 65Cxx boards should use the PHI2(in) for the system clock source.

Daryl

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