Going back to the SBC3 computer (
http://sbc.rictor.org/info3.html), I have a few questions.
On the CPLD it appears the data bus is mapped to "MDATA" (RAM data bus). So the data bus from the MPU (D7:D0) is sent into the CPLD and then the CPLD has ANOTHER data bus (MD7:MD0) that goes to RAM, EEPROM, etc.
What is the purpose of this?
I understand that on the '816, the data bus is a multiplexed address bus for RAM > 64K. But why couldn't the data bus (D7:D0) just go to all of the RAM/EEPROM/etc. directly and save 8 pins by not using MD7:MD0?
Thanks