Going back to the SBC3 computer (http://sbc.rictor.org/info3.html), I have a few questions.

On the CPLD it appears the data bus is mapped to "MDATA" (RAM data bus). So the data bus from the MPU (D7:D0) is sent into the CPLD and then the CPLD has ANOTHER data bus (MD7:MD0) that goes to RAM, EEPROM, etc.

What is the purpose of this?

I understand that on the '816, the data bus is a multiplexed address bus for RAM > 64K. But why couldn't the data bus (D7:D0) just go to all of the RAM/EEPROM/etc. directly and save 8 pins by not using MD7:MD0?

Thanks

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Cat; the other white meat.

The CPLD is also a video generator and drives the MD bus during the PHI2 low period. At the same time, the CPLD is latching the upper address bits from the D data bus. The CPLD is essentially a buffer between the two buses.

Hope that helps!

Daryl

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