Hi all,

So I was just patching a data transfer routine to insert a delay which had been forgotten. I'd freed 5 bytes into which a delay of 13 cycles had to be coded. As everything except Y was available this was straightforward:
Then I remembered from somewhere that some later MPUs could write back the shifted value on the fifth cycle and skip the sixth, while the ALU updates the flags in parallel, but INC and DEC have to go through the ALU; so to be sure of a consistent delay I plumped for INC, which also preserves C.

Browsing the datasheets hasn't revealed any parts with this speed-up; but to rule out the chips this code might run on, do you know which, if any, do? At this point I'm not sure where I got the idea.

Thanks,

Greg

Perhaps check this section of Bruce's doc on the C02

7. Instructions with different cycle counts

Thanks for your reference and quick reply, you've encouraged me to look deeper.

Now I see that the MOS 65CE02 spends 5 cycles on LSR abs but 5 on INC abs as well. The WDC 65C02S says 6 cycles for both. GTE G65SC02-A concurs, with 6 cycles each, as does the G65SC802. So which one is this mysterious chip?