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barnacle
PostPosted: Mon Mar 11, 2024 9:16 pm 
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Hmm. The ZIF adaptor for the tsop-48 flash chips is a bit of a pain: through hole fixing with 1.5mm between adjacent pins, 0.5mm offset between each row of pins, and 2.54mm between rows of pins. It makes sense, I suppose, the pins align with the 0.5mm spacing of the chip, but it means things get thoroughly stirred up, and it's too tight to run a trace between the pins.

Attachment:
progadapt.png
progadapt.png [ 130.94 KiB | Viewed 2041 times ]


Not helped by the courtesy details that neither the Nucleo nor the JEDEC approved flash organise their pins in logical groups.

Neil
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GARTHWILSON
PostPosted: Mon Mar 11, 2024 9:43 pm 
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barnacle wrote:
and it's too tight to run a trace between the pins.

Does your CAD let you make the pads oblong, to make some room between them?

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barnacle
PostPosted: Mon Mar 11, 2024 9:51 pm 
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Yes, it does, but it doesn't really help... the spacing is 1.5mm and the hole 0.7, so even with just an 0.2 width there's just 0.4mm between adjacent lands. I'm not comfortable making the hole surround any thinner than that (and I suspect the pcb maker would complain).

I tend to use an 0.2mm/8 thou track with 0.2mm clearance. I could go finer, I suppose.

Neil
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GARTHWILSON
PostPosted: Tue Mar 12, 2024 12:13 am 
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Hmmm...  .7mm hole is .0276", probably like .0316" before thru-plating reduces its diameter, and there's a little tolerance in the drilling accuracy too, as the bit could wander slightly before getting started.  1.5mm hole separation is .059".  I never go for less than .010" (.25mm) annular ring where a trace comes to the pad, because you lose some reliability if the trace just falls down into the hole; but you could make the anular ring .005" (.12mm) on the sides where traces won't be coming to the pad, and still leave it greater on the ends where traces do connect; then you could have .059"-.0276"-(2*.005")=.0214" (ie, .544mm), enough to get a .006" trace through with nearly .008" clearance on each side, which is within the manufacturing capabilities of all the board houses without charging extra, and there won't be any breakouts in the drilling either.  (In my work, I'm always trying to get the maximum possible density without incurring extra costs.)  I often shave pads too, like this, from the bit-I/O module shown on the front page of my site:


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WM3AbitIOshavedPads.gif
WM3AbitIOshavedPads.gif [ 39.42 KiB | Viewed 2029 times ]

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barnacle
PostPosted: Tue Mar 12, 2024 6:08 am 
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I'm not sure that Kicad offers an easy way to do that to a pad; I think you'd have to draw each instance individually as a specific pad type.

But anyway, it all fits. And when using the part as an 8-bit prom, unless I need half a meg, which is unlikely at the moment, a lot of those pins are held to ground or Vcc, or not used. There are nineteen address lines, plus one data line which is used as a low/high byte selector if you choose to use it (so the flash can deliver 512k 16-bit words, 1024k 8-bit bytes using the selector, or just 512k 8-bit words if the selector and the high bits are ignored).

Now I need to think about how to program it :mrgreen:

Neil
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barnacle
PostPosted: Tue Mar 12, 2024 9:08 am 
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It turns out to be easy to make a tsop48-zip to DIP28 adaptor, so the S29 can impersonate a 28C256 (using the lower 8 bits of the 16 bit data and setting the top bits of the address to zero).

Attachment:
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Neil
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