Hello,
I'm planing to use an AVR to connect a PS2 keyboard (and maybe later on also a SD card) to my 6502 system.
What came in my mind is: Whenever i detect a key pressed on the keyboard the AVR should store the corresponding value in a predefined location in RAM. For this i would like to halt the 6502, store my stuff in memory and let the 6502 run again.

So i would pull the RDY signal low, which makes the CPU halt.
The question is: Do i also have to pull BE signal low to be sure the 6502 releases the bus? Is there a short delay needed?

Is this a good idea in general?
Thanks for any help!

Yes, BE would be needed. The RDY pin can also be used to pause the 65C02 in the middle of a read or write, where the point is that the device on the bus being accessed needs the select to be valid for longer than the normal PHI2 bus cycle allows, so when used on its own, the address bus will continue to be driven.

The current W65C02 datasheet says that BE is asynchronous, so I guess the issue is the setup and hold times.

The current W65C02 datasheet gives a minimum 25ns setup at +5v from BE rising until valid data can be read or written (tBVD), 30ns setup at 3.3v/3.0v (p. 25). It doesn't show time to bus high impedance, but a note says that (maybe it would be called "tBHE" if it was specified in the table) should be similar to the tBVD.