Hello,

The question applies to HuC6280 derivative which has separate /RD & /WR signals.

Maybe I'm asking a very common question but it's not clear what are the timings while performing a read operation.

At which point is the data bus sampled: at the middle of /RD low or while /RD is transitioning from low to high?

On classical 6502 there is a common R/nW signal and sampling of data bus is done asynchronously after the address has stabilized, so the 6502 model most likely does not apply to HuC6280.

Thx.

I would expect the CPU to sample the databus on the clock edge. The read and write controls would also be controlled by the clock edge, but will of course lag slightly.

But the real answer will be in a datasheet.

Hello, PierreGTT. I wasn't able to find a HuC6280 datasheet for confirmation, but I think we can safely conclude that the 6502 model does apply.

Very often a 6502 computer will include external logic like that shown below. Using two NANDs and an inverter, it generates /WR (an active-low pulse suitable for driving the /WE input of a static RAM, for example) and /RD (an active-low pulse suitable for driving the /OE input of a ROM or a static RAM, for example).
Instead, the HuC6280 appears to generate the /RD and /WR signals internally. I believe that's the only difference -- IOW, I don't suppose there's any fundamental timing difference between HuC6280 and 6502.

( FWIW, Wikipedia's HuC6280 page led me to this circuit diagram, which shows /OE and /WE of a static RAM being driven directly from two pins on a HuC6280 marked *RD and *WR.)

Just a reminder... the 6502's R/W signal gets updated early in the cycle, just as the address lines do. At first they're all in flux, and cannot be relied upon. Then after they've become valid, PHI2 (the clock signal) rises and, after further delay, the data bus eventually become valid. The data transfer ends when PHI2 falls. Data is required to become valid shortly before PHI2 falls, satisfying the spec for data setup time. It is also required to remain valid for a short time after PHI2 falls, satisfying the spec for data hold time. Hope this helps...

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Thx!

Yes, it helps.

As you suggest, sampling (storage of value from data bus) shall be done on a clock edge due to synchronous internal design of the CPU (registers change accordingly to a clock edge). Also, sampling the bus on the rising edge of the /OE would be risky because a memory chip will turn its bus in high impedance "as fast as possibly" after /OE is released and data consistency couldn't be guaranteed that way.

If this kind a NAND gates based circuit is implemented within HuC6280, on each clock cycle there should be one /WR and one /RD pulse and for multiple cycle instructions, there will be several /RD & /WR pulses even if there is no access to external ressources.

I think you mean "one /WR or one /RD pulse." And yes, that's the behavior that results from connecting a 6502 to the circuit shown. I suspect the HuC6280's /RD and /WR pins behave the same.

Yup, that's right. Every cycle will produce either a /RD pulse or a /WR pulse. And every cycle falls into one of three categories. Either the chip needs to read memory, it needs to write memory, or else it has an ALU operation to complete (internally) and it doesn't require any memory access at all.

In the latter case you might suppose that no pulse occurs, but instead the 6502 will do a read... and simply ignore the data that gets returned. This is simpler than providing some mechanism to suppress the unneeded access.

Some CPUs do use synchronous internal design, and there's only one meaningful clock edge per cycle. But older chips including the 6800 and 6502 respond to two meaningful clock edges per cycle (as described in the final paragraph of my previous post). I find it helpful to think of every cycle as being a little two-step (or maybe a one-two punch)!

Yes the memory chip will set its bus to high impedance, but sampling the bus on the rising edge of the /OE is not risky, because each of the eight bus lines acts like a small capacitor. So, the data which the chip has driven onto the bus tends to stay there, either until the capacitor eventually bleeds dry (which happen slowly) or until some other device puts new data on the bus.

Do you have goal or project in mind, BTW? If so, pls explain, as it'll be helpful for the discussion.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Thx again



Yes I meant /RD OR /WR low. As the polarity of r/nW does not change over one clock cycle it cannot be both /RD and /WR activated on the same clock cycle.



Moreover, all instructions, even NOP, will trigger an external read due to the cacheless nature of 6502/HuC6280 (each instruction fed from external RAM/ROM).

The project I am working on is a Multi-ROM/CDROM emulator for the PC-engine (see picture). The issue is now solved and was due to not latching the /WR signal which toggles asynchronously to the FPGA's internal clock, and caused inconsistency when CLK rising edge arrived to close to /WR change.