Joined: Thu May 28, 2009 9:46 pm
Posts: 8514
Location: Midwestern USA
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Something that I have been closely studying is the topic of wait-state generation. My interest is fueled by the desire to get my POC V2 unit to run as fast as possible (20 MHz would be great). POC V2 has a number of hardware features that complicate wait-stating, and units built by some others here may well have the same characteristics. Before continuing, please note that this discussion is specific to the WDC versions of the 65C02 and 65C816. My theories should be applicable to non-WDC 65C02s, but as I don't have anything powered by one of those processors, I can't prove that to be the case.
The 6502 family since inception has had the RDY input to stop the processor for an arbitrary amount of time. In simple terms, as long as RDY is held high the MPU will run and execute instructions. When RDY is brought low the MPU will stop, with a caveat—the NMOS family does not respond to RDY during a write cycle. In the case of the WDC MPUs, negating RDY causes the MPU to stop on the next high-to-low Ø2 transition—the MPU's internal clock will remain in the high state once it has stopped. When RDY has been driven high the MPU will restart on the next high-to-low Ø2 transition.
While RDY is low and the MPU is stopped, all registers will be maintained in the state they were in at the time RDY was driven low. Also, all outputs, such as the address bus, RWB, etc., will be maintained as though the Ø2 clock had been stopped in the high phase. Implied by this is the 65C816 will be using the data bus for data purposes, not extended addressing. There is no limit as to how long the MPU can be stopped with RDY.
Some interesting design problems can arise with the use of RDY for wait-stating. Consider the following circuit, which is used to generate read and write signals for hardware that have separate /OE (output-enable) and /WE (write-enable) inputs:
Attachment:
File comment: Ø2-Qualified Read/Write Circuit
read_write_qualify_alt.gif [ 46.98 KiB | Viewed 13912 times ]
In studying the above circuit's logic, it can be seen that neither /RD (read data) or /WD (write data) can be driven low ("asserted") unless Ø2 (netlist symbol PHI2) is high, which is when the data bus would have valid content. That's all well and good—until the MPU is stopped with RDY. Although the MPU will maintain the state of RWB (high if reading, low if writing) while halted, the above circuit will "malfunction." Each time Ø2 goes low, /RD or /WD will be de-asserted, and when Ø2 goes high again, asserted. The potential for the addressed device to get confused by the oscillating /RD or /WD signal will be high.
Another case in which trouble can arise is one in which Ø2 is used to qualify chip selects, for example:
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File comment: Ø2-Qualfied Decoding Circuit
wilson_decode.gif [ 174.81 KiB | Viewed 13912 times ]
The above circuit was copied from Garth Wilson's website. Note the chip select (/CS) to the RAM, which is not asserted unless Ø2 is high and A15 is low. If A15 is low while the MPU has been wait-stated with RDY, that chip select will synchronously oscillate with Ø2, causing the RAM to be repeatedly deselected and selected.
A third case that is specific to the 65C816 is the generation of the A16-A23 address bits, which appear on the data bus during Ø2 low. Here's an example generator circuit:
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File comment: 65C816 A16-A23 Address Generation
extended_address_generation.gif [ 24.63 KiB | Viewed 13912 times ]
During Ø2 low (PHI1 high), the eight latches in the 74AC573 octal D-type transparent latch will be opened, causing the Q outputs to follow the D inputs. Since it is during Ø2 low that the 65C816 emits the bank bits, the Qs will reflect the bank address. When Ø2 makes a low-to-high transition, the latches will close and the '573 will maintain the extended address on its Qs. At the same time, the 65C816 will cease driving the bank bits onto D0-D7 and instead will start treating D0-D7 as a data bus.
If after latching the bank address, the MPU is stopped with RDY, an unfortunate situation will arise on the next fall of Ø2. The '573 will open its latches, again causing the Qs to follow the Ds. However, the data bus at that time will reflect data, not bank bits, and when Ø2 goes high again and the latches close, A16-A23 will contain the data bus bit patterns, not the previously-captured bank bits, resulting in a wrong address being given to the system.
Given the above scenarios (and there are some others that are similar), it almost seems as though use of RDY will create problems, not solve them, particularly if a 65C816 is powering the system. During the design of my POC V2.2 unit, I came to the realization that any attempt at wait-stating involving the use of RDY would run into two of the above cases, and I would have a unit that would not properly operate. That realization caused me to stop design work and cogitate on developing a good method of wait-stating.
As I noted above, the 'C02 and '816 internally stop their clocks in the high phase upon responding to a low on RDY. A corollary to that characteristic is to be found in a small note buried in the data sheet:PHI2 can be held in either high or low state to preserve the contents of internal registers since the microprocessor is a fully static design. The above is from the 65C02 data sheet. The 65C816 data sheet has a similar note:PHI2 can be held in either state to preserve the contents of internal registers and reduce power as a Standby mode. In other words, it is possible to halt either MPU without detriment by simply halting the clock. Since a wait-state induced via negation of RDY halts the MPU in the Ø2 high phase, it can be surmised that externally stopping Ø2 in the high phase should accomplish the exact same thing as using RDY. However, since it would be the clock generator that would be stopped, not just the MPU, anything slaved to the clock, such as the aforementioned read/write, chip select, and extended address circuits, would likewise stop and maintain their state.
Hence the objective will be to concoct a glitch-free method of halting Ø2 in the high phase and simultaneously halting Ø1 in the low phase. Just how would this be accomplished? I'll present my ideas in the next post.
_________________ x86? We ain't got no x86. We don't NEED no stinking x86!
Last edited by BigDumbDinosaur on Sun Oct 24, 2021 7:10 pm, edited 3 times in total.
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