6502.org Forum Projects Code Documents Tools Forum
It is currently Mon May 13, 2024 9:11 pm

View unanswered posts | View active topics


Board index » 6502.org Users Forum » Hardware

All times are UTC




Post new topic Reply to topic  Page 2 of 2
  [ 23 posts ]  Go to page Previous  1, 2
  Previous topic | Next topic 
Author Message
Michael
PostPosted: Sat Oct 21, 2023 7:16 pm 
Offline
User avatar

Joined: Wed Feb 13, 2013 1:38 pm
Posts: 586
Location: Michigan, USA
Using a single cycle $03 opcode works quite well, Bill. A simple and clever way to end up in a sync cycle after a reset sequence without having to worry about how many cycles are required for the sequence. Just tested it on my production board by sending ten $03 bytes after taking reset high so the 6502 PC should be near $303 after the reset sequence...

Code:
  /******************************************************************************
   *  core 'blind interface' functions                                          *
   *                                                                            */
   void uReset()                      // ****************************************
   { byte i = 10;                     //
     clk(1);                          // clock hi
     res(0);                          // reset = 0, start reset sequence
     uPull(ram); uPull(ram);          // send a couple clocks while reset lo
     res(1);                          // reset = 1
     do                               // push ten $03 bytes
     { uPush(0x03);                   //  "
     } while(i--);                    //  "
   }                                  //


Attachments:
6502 busmeister.png
6502 busmeister.png [ 58.36 KiB | Viewed 8923 times ]
easyeda build #2.png
easyeda build #2.png [ 1.83 MiB | Viewed 8923 times ]
Top
 Profile  
Reply with quote  
BigEd
PostPosted: Sat Oct 21, 2023 7:20 pm 
Offline
User avatar

Joined: Thu Dec 11, 2008 1:28 pm
Posts: 10800
Location: England
Is there no way to sync up using only legit opcodes?
Top
 Profile  
Reply with quote  
Michael
PostPosted: Sat Oct 21, 2023 7:38 pm 
Offline
User avatar

Joined: Wed Feb 13, 2013 1:38 pm
Posts: 586
Location: Michigan, USA
... good question...


Last edited by Michael on Sun Oct 22, 2023 5:17 am, edited 1 time in total.

Top
 Profile  
Reply with quote  
gfoot
PostPosted: Sat Oct 21, 2023 9:37 pm 
Offline

Joined: Fri Jul 09, 2021 10:12 pm
Posts: 741
BigEd wrote:
Is there no way to sync up using only legit opcodes?

How about PHA then NOP and a hi-Z cycle? If sync is on PHA then the NOP is ignored and the third cycle is a write by the CPU. If sync is on NOP then it's a NOP and the bus floats for the third cycle but it's ignored. Either way there'll be a sync on the fourth cycle. You can either issue the PHA at the earliest time the reset might be complete, or precede it with some 2-cycle NOPs to protect against being in the middle of a possibly longer instruction.

If the third cycle bring a write is a problem then maybe LDA <zp> would be OK in its place.
Top
 Profile  
Reply with quote  
BruceRMcF
PostPosted: Sat Oct 21, 2023 10:20 pm 
Offline

Joined: Wed Aug 21, 2019 6:10 pm
Posts: 217
gfoot wrote:
BigEd wrote:
Is there no way to sync up using only legit opcodes?
...

If the third cycle bring a write is a problem then maybe LDA <zp> would be OK in its place.


What if you repeated "LDA $EA" ... since $EA is NOP, if you start in the middle of a LDA $EA, it's a NOP and you start at the beginning of the next "LDA $EA".

Edit: I am not a hardware hand, but since that is repeated %1010.1001 %1110.1010, which is %[11][01][11][00].[11][00][01][10], it seems a tri-state driver with DRIVE_Q0-7 on the Data Bus, with /DRIVE_OE on being in the start-up mode, and wiring DRIVE_D2,D4 to GND and DRIVE_D3,D5,D7 to VCC gets you part of the way there. It seems a toggling flip flop driven by PHI2 with its Q inputting DRIVE_D1,D6 and /Q inputting DRIVE_D0 would get you there. IIUC, you can wire up a 7400 to do a toggling flip flop on PHI2=H.


Last edited by BruceRMcF on Mon Oct 23, 2023 3:37 pm, edited 2 times in total.

Top
 Profile  
Reply with quote  
gfoot
PostPosted: Sat Oct 21, 2023 10:55 pm 
Offline

Joined: Fri Jul 09, 2021 10:12 pm
Posts: 741
Yes exactly. Another option that's interesting regarding Jeff's minimal 3 wire system (which I'm hoping to get back to tomorrow) is 6xEA, 00, 6xEA. The first six EAs ensure that either the 00 is an opcode fetch (and we execute a BRK sequence of seven cycles), or the EA afterwards is an opcode fetch and we execute three NOPs. Either way, the next cycle after this sequence will be an opcode fetch. (With Jeff's latest scheme the two-cycle instruction is not actually NOP, but any two cycle instruction is fine there.)
Top
 Profile  
Reply with quote  
tius
PostPosted: Mon Oct 23, 2023 10:13 pm 
Offline
User avatar

Joined: Fri Nov 05, 2021 1:06 pm
Posts: 20
Michael wrote:
The clock and reset transition timing does make a difference. I can consistently force a 7 cycle or 8 cycle sequence by setting the reset pin during the hi or lo portion of PHI2, respectively. That's why I'm curious about your hardware.


Dear Michael, the different behaviour with my board gave me no peace. I have simplified the experimental setup and only feed in RESB and PHI2 with a minimal programme and check the level of VPB after each step.

If the rising edge of RESB occurs during the low phase of PHI2, I always get the same result:
Code:
  1  resb H  phi2 H  vpb H
  2  resb L  phi2 H  vpb H
  3  resb L  phi2 L  vpb H
  4  resb L  phi2 H  vpb H
  5  resb L  phi2 L  vpb H
  6  resb L  phi2 H  vpb H
  7  resb L  phi2 L  vpb H
  8  resb L  phi2 H  vpb H
  9  resb L  phi2 L  vpb H
 10  resb H  phi2 L  vpb H
 11  resb H  phi2 H  vpb H
 12  resb H  phi2 L  vpb H
 13  resb H  phi2 H  vpb H
 14  resb H  phi2 L  vpb H
 15  resb H  phi2 H  vpb H
 16  resb H  phi2 L  vpb H
 17  resb H  phi2 H  vpb H
 18  resb H  phi2 L  vpb H
 19  resb H  phi2 H  vpb H
 20  resb H  phi2 L  vpb H
 21  resb H  phi2 H  vpb H
 22  resb H  phi2 L  vpb H
 23  resb H  phi2 H  vpb H
 24  resb H  phi2 L  vpb L
 25  resb H  phi2 H  vpb L
 26  resb H  phi2 L  vpb L
 27  resb H  phi2 H  vpb L
 28  resb H  phi2 L  vpb H
 29  resb H  phi2 H  vpb H
 30  resb H  phi2 L  vpb H
 31  resb H  phi2 H  vpb H
 32  resb H  phi2 L  vpb H
 33  resb H  phi2 H  vpb H
vpb low in step 24


If the rising edge of RESB occurs during the high phase, the result varies:
Code:
  1  resb H  phi2 H  vpb H
  2  resb L  phi2 H  vpb H
  3  resb L  phi2 L  vpb H
  4  resb L  phi2 H  vpb H
  5  resb L  phi2 L  vpb H
  6  resb L  phi2 H  vpb H
  7  resb L  phi2 L  vpb H
  8  resb L  phi2 H  vpb H
  9  resb H  phi2 H  vpb H
 10  resb H  phi2 L  vpb H
 11  resb H  phi2 H  vpb H
 12  resb H  phi2 L  vpb H
 13  resb H  phi2 H  vpb H
 14  resb H  phi2 L  vpb H
 15  resb H  phi2 H  vpb H
 16  resb H  phi2 L  vpb H
 17  resb H  phi2 H  vpb H
 18  resb H  phi2 L  vpb H
 19  resb H  phi2 H  vpb H
 20  resb H  phi2 L  vpb L
 21  resb H  phi2 H  vpb L
 22  resb H  phi2 L  vpb L
 23  resb H  phi2 H  vpb L
 24  resb H  phi2 L  vpb H
 25  resb H  phi2 H  vpb H
 26  resb H  phi2 L  vpb H
 27  resb H  phi2 H  vpb H
 28  resb H  phi2 L  vpb H
 29  resb H  phi2 H  vpb H
 30  resb H  phi2 L  vpb H
 31  resb H  phi2 H  vpb H
 32  resb H  phi2 L  vpb H
 33  resb H  phi2 H  vpb H
vpb low in step 20

  1  resb H  phi2 H  vpb H
  2  resb L  phi2 H  vpb H
  3  resb L  phi2 L  vpb H
  4  resb L  phi2 H  vpb H
  5  resb L  phi2 L  vpb H
  6  resb L  phi2 H  vpb H
  7  resb L  phi2 L  vpb H
  8  resb L  phi2 H  vpb H
  9  resb H  phi2 H  vpb H
 10  resb H  phi2 L  vpb H
 11  resb H  phi2 H  vpb H
 12  resb H  phi2 L  vpb H
 13  resb H  phi2 H  vpb H
 14  resb H  phi2 L  vpb H
 15  resb H  phi2 H  vpb H
 16  resb H  phi2 L  vpb H
 17  resb H  phi2 H  vpb H
 18  resb H  phi2 L  vpb H
 19  resb H  phi2 H  vpb H
 20  resb H  phi2 L  vpb H
 21  resb H  phi2 H  vpb H
 22  resb H  phi2 L  vpb L
 23  resb H  phi2 H  vpb L
 24  resb H  phi2 L  vpb L
 25  resb H  phi2 H  vpb L
 26  resb H  phi2 L  vpb H
 27  resb H  phi2 H  vpb H
 28  resb H  phi2 L  vpb H
 29  resb H  phi2 H  vpb H
 30  resb H  phi2 L  vpb H
 31  resb H  phi2 H  vpb H
 32  resb H  phi2 L  vpb H
 33  resb H  phi2 H  vpb H
vpb low in step 22


Repeating the two experiment several times gives the same results:
Code:
vpb low in step 24
vpb low in step 24
vpb low in step 24
vpb low in step 24
vpb low in step 24
vpb low in step 24
vpb low in step 24
vpb low in step 24
vpb low in step 24
vpb low in step 24
vpb low in step 24
vpb low in step 24
vpb low in step 24
vpb low in step 24
vpb low in step 24
vpb low in step 24
vpb low in step 24
vpb low in step 24
vpb low in step 24
vpb low in step 24


Code:
vpb low in step 22
vpb low in step 20
vpb low in step 20
vpb low in step 20
vpb low in step 20
vpb low in step 20
vpb low in step 20
vpb low in step 20
vpb low in step 22
vpb low in step 20
vpb low in step 22
vpb low in step 22
vpb low in step 22
vpb low in step 22
vpb low in step 22
vpb low in step 20
vpb low in step 20
vpb low in step 22
vpb low in step 22
vpb low in step 22


If I have understood you correctly, these variations do not appear in your set-up? This seems very strange to me. Sorry if I have mixed things up!


Last edited by tius on Tue Oct 24, 2023 9:38 am, edited 1 time in total.

Top
 Profile  
Reply with quote  
tius
PostPosted: Mon Oct 23, 2023 10:29 pm 
Offline
User avatar

Joined: Fri Nov 05, 2021 1:06 pm
Posts: 20
BruceRMcF wrote:
gfoot wrote:
BigEd wrote:
Is there no way to sync up using only legit opcodes?
...

...
What if you repeated "LDA $EA" ... since $EA is NOP, if you start in the middle of a LDA $EA, it's a NOP and you start at the beginning of the next "LDA $EA".
...


$A9 $EA seems like a very good idea to me. However, my system seems to behave completely predictably if the rising edge of RESB occurs during PHI2 low.

To be on the safe side, I passively check the data bus for the expected values during write commands. If the feed were not synchronous, this should be noticed immediately at this point and I can repeat the reset sequence.

Or am I missing something?
Top
 Profile  
Reply with quote  
Display posts from previous:  Sort by  
Post new topic Reply to topic  Page 2 of 2
  [ 23 posts ]  Go to page Previous  1, 2

Board index » 6502.org Users Forum » Hardware

All times are UTC


Who is online

Users browsing this forum: qookie and 11 guests

You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to:  
6502.org is an ongoing project by Mike Naberezny and contributors.