Looking at a loadable 4bit binary counter again, it seems like a 74193 is most of the state machine needed to write a byte loaded into a part of USR's (that is, 74299). If $B is loaded into the counter, then QA, which is driving /RAM_WR, and QB, which is driving /RAM_CS as well as /AL_USR_OE1 and /DATA_USR_OE1, both start high. On the next clock pulse, they both go low. On the next clock pulse, the /RAM_WR goes high, completing the write, with /AL_USR_OE1 still low for the data hold when the ram is written. The next clock cycle raises /RAM_CS and the /AL_USR_OE1, and the next clock cycle brings the counter to $FF, so the /COUNT_OC overflow carry is pulsed. That pulse is used to clear the USR's, which then clears the framing bit in COUNT2_Q7, ending the state.
So the counter clock runs while the framing bit is high, which can be done by an AND of the framing bit with the system clock. So that adds a quad (positive) 2-input AND like a 7408 to the parts list.
COUNT2_UP := AND(AL_USR_Q7,PHI2)
IIUC, the /COUNT2_LOAD acts as a transparent latch does, so the framing bit can be used to drive the load ... it will be low the entire time that the counter is not running, but the load value is static.
COUNT2_A := COUNT2_C := COUNT2_D := VCC
COUNT2_B := GND
/COUNT2_LOAD := AL_USR_Q7
The carry overflow has to reset the USR's to clear the framing bit and bring an end to the write data state. And the USR's also have to be cleared when /Reset is pulsed. From the 299 datasheet, that is an active low master reset:
/AL_USR_MR := /DATA_USR_MR := AND(/COUNT2_CO,/RESET_INPUT)
An /S /R flip flop "SR1" can provide the bus release needed for the 1st stage bootloader by driving 6502_BE low, with the bus returned when bit 6 if the address/framing byte is high. A dual /S /R flip flop is handy because the other can be used by the Flash Read Command state machine (and if a dual flip flop of the correct family is not in stock, it can always be replaced by a 7400 wired correctly). Two gates of a hex , plus the two remaining gates of the AND can be used to filter for the Flash SCLK, so it only runs when in the BOOT period, which is when the /SR2_Q is high, and only runs when the FRAME bit is low:
/SR2_R := /RESET_INPUT
/SR2_S := NOT(/AL_USR_IO6)
/FRAME := NOT(AL_USR_Q7)
BOOT_SCLK := AND(PHI2,/SR2_Q)
FLASH_SCLK := AND(BOOT_SCLK,/FRAME)
Using a /S /R flip flop to drive the Flash SI to write the Read command and address means that the counter can be left to run freely, as additional /BO pulses will be ignored. A countdown from 5 started when the FLASH_SCLK starts running will generate the /BO pulse after the 6th SCLK pulse:
/COUNT1_LOAD := /RESET_INPUT
COUNT1_DOWN := FLASH_SCLK
COUNT1_A := COUNT1_C := VCC
COUNT1_B := COUNT1_D := GND
/SR1_R := /RESET_INPUT
/SR1_S := /COUNT1_BO
SR1_Q =: FLASH_SI
So:
- The (debounced) /RESET_INPUT clears the USR's, which brings the FRAME bit low. It also resets the /BE master flip flop and the FLASH_SI flip flop, which places 0 on the FLASH_SI pin and starts the FLASH_SCLK running.
- After six FLASH_SCLK pulses, COUNT1 pulses its /borrow pin, which sets the FLASH_SI flipflop high, generating the $03h READ command and the $FFFFFF data address.
- While the read command and address has been written to the FLASH, FLASH_SO has been pulled down by ground through a resister, so AL_USR_Q7 remains low, so the FLASH_SCLK and USR's keep running. This continues through the first byte of data of $00 at the (likely mirrored) $FFFFFF address, which then wraps around to $000000, where pairs of frame/address and data bytes, %10aaaaaa %dddddddd are located.
- After sixteen cycles of loading serial data, AL_USR_Q7 goes high when the frame bit is shifted in. This pauses the FLASH_SCLK and starts the COUNT2 count-up clock. The loaded value drives the write cycle, with USR outputs enable, on the COUNT_QA and COUNT_QB pins. When the counter reaches $F, the /CO pulse clears the USR's, dropping AL_USR_Q7, halting the COUNT clock and starting the FLASH_SCLK again
- This continues until the final address frame byte of %11xxxxxx %xxxxxxxx, so reasonably $FF, which /Sets the master flipflop, drives BE up, and halts the FLASH_SCLK until the next /RESET_INPUT.
Or at least, something along those lines. For instance, if gate latencies means that the timing of the /CO pulse for the Read command is early or late, that can be fixed by shifting the COUNT1_A-D inputs until it hits at the right cycle.
So:
- One FlashROM
- Two 74x299 tri-state Universal Shift Registers
- Two 74x193 counters
- A 74x279 dual /S /R flip flop, or 74x00 quad NAND
- A 74x08 quad, 2-input AND
- One hex inverter or a 74x00 and heaps of pullup/pulldown resisters
If 5v, the USR's need to accept TTL levels for a 3.3V FlashROM SO signal, and a voltage bridge for the FlashROM SCLK, SI and /SELECT.
A CPLD would of course be more compact. This would be at least a couple of breadboards if breadboarding -- if done to replace the ROM in the single broadboard 6507/RIOT SBC, it would make it a three or four breadboard SBC -- but if done with SMB, maybe it's compact enough.