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Data bus logging at higher clock speeds

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gfoot

Post subject: Data bus logging at higher clock speeds

Posted: Thu Aug 03, 2023 5:28 pm

Joined: Fri Jul 09, 2021 10:12 pm
Posts: 741

To help with debugging, I'm looking for a good (and cheap!) way to analyse the 6502's bus at a high clock speed - up to 50MHz or so. Hoglet's decoder (https://github.com/hoglet67/6502Decoder/wiki) combined with his suggested cheap logic analyser (https://www.instructables.com/FX2LP-CY7 ... -Analyzer/) is a great combination, but the logic analyser has a limited sampling rate and I'm going to want to go at least a bit higher than that.

Other than buying a more expensive logic analyser, my first thought was to build something to record the bus activity to fast RAM, and then play it back later at a slower rate. I have plenty of 71256-12 SRAM chips, and coupling one of these with 16 bits of counters should do most of what's required. Hoglet's decoder works remarkably well with only a data bus trace, so just 8 bit wide recording should be fine.

But before going down another rabbit hole of reinvented wheels, I thought I'd ask in case you guys have hardware (bought or built) that already does a good job of this?

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BigEd

Post subject: Re: Data bus logging at higher clock speeds

Posted: Thu Aug 03, 2023 5:47 pm

Joined: Thu Dec 11, 2008 1:28 pm
Posts: 10800
Location: England

I'm supposing you're using the analyser in synchronous mode, with the 6502's own clock? I believe that gets you to higher frequencies, although perhaps not as high as you are looking for.

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akohlbecker

Post subject: Re: Data bus logging at higher clock speeds

Posted: Thu Aug 03, 2023 7:16 pm

Joined: Sat Jul 24, 2021 1:37 pm
Posts: 282

Best idea I've found so far is a FTDI USB-to-SPI at 10MHz, and a SPI-to-GPIO like the MCP23S17. That should get you to around 1MB/s, similar to the logic analyzer you linked.

Logging it to SRAM via a dedicated circuit synchronous with the clock is a novel and interesting idea, I don't think I've seen it built before!

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gfoot

Post subject: Re: Data bus logging at higher clock speeds

Posted: Thu Aug 03, 2023 10:33 pm

Joined: Fri Jul 09, 2021 10:12 pm
Posts: 741

BigEd wrote:

I'm supposing you're using the analyser in synchronous mode, with the 6502's own clock? I believe that gets you to higher frequencies, although perhaps not as high as you are looking for.

I don't actually remember! I need to read hoglet's thread again really.

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allisonlastname

Post subject: Re: Data bus logging at higher clock speeds

Posted: Thu Aug 03, 2023 11:59 pm

Joined: Mon Mar 06, 2023 9:26 am
Posts: 88
Location: UK

With 4 ram chips (or 1 and some complicated circuitry) you could theoretically log the entire bus state every cycle. Complete overkill, but good for bragging rights

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gfoot

Post subject: Re: Data bus logging at higher clock speeds

Posted: Fri Aug 04, 2023 12:37 am

Joined: Fri Jul 09, 2021 10:12 pm
Posts: 741

Haha yes. But connecting up a large number of bus lines is an error-prone chore, with the chance of a loose wire or bad connection being much higher. The hoglet decoder's best feature is that it works well with so few signals being logged.

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hoglet

Post subject: Re: Data bus logging at higher clock speeds

Posted: Fri Aug 04, 2023 8:43 am

Joined: Sun Jun 29, 2014 5:42 am
Posts: 337

A couple of thoughts here....

The FX2 dev board will run at upto 12MHz in 16-bit wide capture, or upto 24MHz in 8-bit wide capture. The limiting factor here is USB-2 speed, as the board doesn't include any capture memory. The decoder will work with just the 8 data bus bits connected, but is not very error resilient in that mode. For your application you really need SYNC connected as well.

If you are getting good traces with CPU speeds beyond 4MHz, then you are likely using the synchronous capture mode already (i.e. using the 6502 clock as an external capture clock for the logic analyzer). Asynchronous capture requires a minimum of ~6x over-sampling.

Capturing at 50MHz, 16-bits wide, goes well beyond USB-2 speeds, and needs either local buffering, or a USB-3 capable chipset.

The cheapest off-the-shelf logic analyzer I know of that will run at these speeds with an external capture clock is the DSLogic Plus:
https://www.dreamsourcelab.com/shop/log ... ogic-plus/
https://www.dreamsourcelab.com/doc/DSLo ... asheet.pdf

This will accept an exteral capture clock at upto 50MHz, and has 256Mbits of capture memory.

These cost about £100 on ebay (beware of fakes though!)

I don't personally have one of these, but it's probably what I would buy.

The other, much less off the shelf, option that comes to mind is the Open Bench Logic Sniffer. This is an open source FPGA based logic analyzer that's got some very flexible triggering options. The original hardware is no longer available, but it might be possible to port this to one of the new Chinese FPGA products, such as the Tang Nano. The Tang Nano 9K includes a 64 Mbit DRAM that is 32-bits wide, so should be capable of streaming data at a very fast rate. The other challenge would be trying to get the data out again over USB. The Tang boards use the BL702 USB UART. The data sheet says the maximum serial speed is 8Mbaud, but I have no idea if this is feasible. There are also no flow control signals connected to the FPGA (i.e. just Tx and Rx).

The Tang Nano 9K costs about £20 (shipped to the UK) and you would need a 16-bit wide level shifter.

Dave

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gfoot

Post subject: Re: Data bus logging at higher clock speeds

Posted: Fri Aug 04, 2023 3:40 pm

Joined: Fri Jul 09, 2021 10:12 pm
Posts: 741

Thanks Dave, that's interesting. The Tang option sounds appealing especially given how much RAM it has, except that given the work involved I'm more confident that I could get the static RAM capture and replay working, and hook the FX2 up to that. I'll think more about how that would work.

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gfoot

Post subject: Re: Data bus logging at higher clock speeds

Posted: Sat Aug 05, 2023 3:24 pm

Joined: Fri Jul 09, 2021 10:12 pm
Posts: 741

Maybe something like this:

Attachment:

File comment: High speed parallel data capture and playback

20230805_160923.jpg [ 4.72 MiB | Viewed 5012 times ]

The microcontroller doesn't need to be very fast, it is just coordinating things. In capture mode the system clock is passed through the multiplexer to the counters, and inverted and passed to the RAM's /WE. The system reset signal can reset the counters. The microcontroller isn't exposed to the high frequency lines but can watch the counters' A15 to spot whether they have rolled over.

After capture, the microcontroller disables the multiplexer so that the system clock no longer drives anything, and it can send its own clock pulse to the counters to reset them, watching A15 to see when they reset and counting the pulse required to see how far the counters had got. If the counters had already wrapped then no rewinding is needed.

For playback the microcontroller just sends more clock pulses until it reaches the end of the recording again.

The logic analyser then just samples the RAM data lines at a frequency driven by the MCU's clock pulses.

ATTINY85 is probably too small for this as it would be nice to have buttons for capture, rewind, and playback, requiring more pins, unless there are some here that could be optimised away with circuit changes. Also it should probably be connected to a signal from the test system to stop capturing when a certain event occurs, e.g. RDY/WAI, or an I/O pin, that software under test can use for signaling. This could also be connected to one of the counter outputs to limit the capture length.

It should be possible to add a second RAM IC without much trouble, to allow longer captures, and a proper PCB/SMD-based implementation could also just use much larger fast memory ICs.

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akohlbecker

Post subject: Re: Data bus logging at higher clock speeds

Posted: Sat Aug 05, 2023 9:32 pm

Joined: Sat Jul 24, 2021 1:37 pm
Posts: 282

Have you considered adding hardware breakpoint support to this? Using a pair of 74HC688 with one side connected to the address bus, and the other side connected to a pair of 74HC595 shift registers. The ATTINY can then set the breakpoint over serial, and with a bit of logic the comparators can stop the clock/capture when a given address is reached.

EDIT: Posted a circuit here viewtopic.php?p=101935#p101935

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gfoot

Post subject: Re: Data bus logging at higher clock speeds

Posted: Sun Aug 06, 2023 12:50 am

Joined: Fri Jul 09, 2021 10:12 pm
Posts: 741

Yes I think that's interesting - however my plan here is to make an external device that's not part of the main computer, nor connected to a PC when in active use - just something you plug between your logic analyzer and the computer to buffer the data and help the logic analyzer, rather than an integral part of the computer circuit itself.

If you built an ATTiny or similar into your mainboard though then I think your idea could work well. You might not even need the ATTiny. You could use debug registers written by the 6502 itself, to set the breakpoint address, for example.

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gfoot

Post subject: Re: Data bus logging at higher clock speeds

Posted: Sun Aug 06, 2023 6:03 am

Joined: Fri Jul 09, 2021 10:12 pm
Posts: 741

This seems to be working pretty well now, here's a video of it in action:

https://drive.google.com/file/d/1Lqhhox ... drive_link

I turned on the computer, and the bus capture circuit is powered from there. It goes a bit crazy at first, but then it sets itself up in an "armed" state, ready to start capturing at the next reset. When I reset the computer, briefly all the data bus LEDs flicker so quickly they appear dim, and when it's captured 32768 or so samples, it switches to playback mode.

For testing purposes I've set it to wait one second between playback samples - the first few are junk from during the CPU's reset sequence (the interrupt-like sequence after /RESET goes high). The program start address is $E000, so after a few seconds you'll see the LED bar display on the right go blank, then show $E0 (for the second time - it shows this value earlier in the reset sequence as well), and then it will show the first few opcodes of the program - $A2, $FF is "LDY #$FF", then $9A is "TXS", and $58 is "CLI".

So it's working pretty well - I need to remember how to use the logic analyser, and hook that up to capture the data at a faster speed and then run it through hoglet's decoder.

Here's the schematic, E&OE as I drew this after building it:

Attachment:

File comment: Fast bus capture schematic

schematic.png [ 62.4 KiB | Viewed 4958 times ]

The microcontroller has two inputs - one from the CPU's /RESET line, the other from the counters' A15 line so it can keep an eye on the count - and two outputs, one that enables/disables recording mode, and another that sends a clock pulse when in playback mode. I replaced the multiplexer with a quad NAND as it's faster, and added a flipflop to track the recording state as the microcontroller is not fast enough to react to the end of the reset signal - so when the microcontroller wants to start capturing, the flipflop delays that until the /RESET rises.

The frequency counter broke badly when I implemented the rest of the code - it's only really possible to run that when recording with a circular buffer, which I haven't implemented fully yet.

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gfoot

Post subject: Re: Data bus logging at higher clock speeds

Posted: Sun Aug 06, 2023 2:00 pm

Joined: Fri Jul 09, 2021 10:12 pm
Posts: 741

I've got it hooked up to the logic analyser now, and it's working to a degree - there are some prediction failures however, either due to my device logging the data wrongly or something to do with the way the logic analyser and decoder are sampling the signal from my device.

To do this I've connected the eight data bits from my device to the logic analyser, along with the clock pulse signal which behaves a lot like phi2 - the counters count up on the rising edge, so sampling the data on the falling edge should be good. The Arduino code is meant to do this at a sedate rate - with at least 10us low and 10us high on every cycle - but I actually had to set the sample rate in sigrok-cli rather high, or it was missing data.

I haven't figured out the method for doing synchronous captures with it yet, but I saw hoglet's posts about that and will try that when I get my head around it! This is an asynchronous capture of my device replaying the log it took from my test program booting up and starting to copy itself to RAM:

Code:

gfoot@box:~/logicanalyzer/6502Decoder$ sigrok-cli -d fx2lafw --config samplerate=500KHz --channels D0,D1,D2,D3,D4,D5,D6,D7,D8 -o data2.bin -O binary --triggers D8=r --samples=1000000

gfoot@box:~/logicanalyzer/6502Decoder$ ./decode6502 -h -s --sync= --rdy= --rst= --rnw= --phi2=8 --vecrst=a2e000 --cpu=65c02 <data2.bin
???? :          : RESET !!       : A=?? X=?? Y=?? SP=?? N=? V=? D=0 I=1 Z=? C=?
E000 : A2 FF    : LDX #FF        : A=?? X=FF Y=?? SP=?? N=1 V=? D=0 I=1 Z=0 C=?
E002 : 9A       : TXS            : A=?? X=FF Y=?? SP=FF N=1 V=? D=0 I=1 Z=0 C=?
E003 : 58       : CLI            : A=?? X=FF Y=?? SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E004 : A0 42    : LDY #42        : A=?? X=FF Y=42 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E006 : B9 1E E0 : LDA E01E,Y     : A=F9 X=FF Y=42 SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E009 : 99 FF FF : STA FFFF,Y     : A=F9 X=FF Y=42 SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E00C : 88       : DEY            : A=F9 X=FF Y=41 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00D : D0 F7    : BNE E006       : A=F9 X=FF Y=41 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E006 : B9 1E E0 : LDA E01E,Y     : A=80 X=FF Y=41 SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E009 : 99 FF FF : STA FFFF,Y     : A=80 X=FF Y=41 SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E00C : 88       : DEY            : A=80 X=FF Y=40 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00D : D0 F7    : BNE E006       : A=80 X=FF Y=40 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E006 : B9 1E E0 : LDA E01E,Y     : A=FF X=FF Y=40 SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E009 : 99 FF FF : STA FFFF,Y     : A=FF X=FF Y=40 SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E00C : 88       : DEY            : A=FF X=FF Y=3F SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00D : D0 F7    : BNE E006       : A=FF X=FF Y=3F SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E006 : B9 1E E0 : LDA E01E,Y     : A=70 X=FF Y=3F SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E009 : 99 FF FF : STA FFFF,Y     : A=70 X=FF Y=3F SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00C : 88       : DEY            : A=70 X=FF Y=3E SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00D : D0 F7    : BNE E006       : A=70 X=FF Y=3E SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E006 : B9 1E E0 : LDA E01E,Y     : A=8E X=FF Y=3E SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E009 : 99 FF FF : STA FFFF,Y     : A=8E X=FF Y=3E SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E00C : 88       : DEY            : A=8E X=FF Y=3D SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00D : D0 F7    : BNE E006       : A=8E X=FF Y=3D SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E006 : B9 1E E0 : LDA E01E,Y     : A=F5 X=FF Y=3D SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E009 : 99 FF FF : STA FFFF,Y     : A=F5 X=FF Y=3D SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E00C : 88       : DEY            : A=F5 X=FF Y=3C SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00D : D0 F7    : BNE E006       : A=F5 X=FF Y=3C SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E006 : B9 1E E0 : LDA E01E,Y     : A=A2 X=FF Y=3C SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E009 : 99 FF FF : STA FFFF,Y     : A=A2 X=FF Y=3C SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E00C : 88       : DEY            : A=A2 X=FF Y=3B SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00D : D0 F7    : BNE E006       : A=A2 X=FF Y=3B SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E006 : B9 1E E0 : LDA E01E,Y     : A=C8 X=FF Y=3B SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E009 : 99 FF FF : STA FFFF,Y     : A=C8 X=FF Y=3B SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E00C : 88       : DEY            : A=C8 X=FF Y=3A SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00D : D0 F7    : BNE E006       : A=C8 X=FF Y=3A SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E006 : B9 1E E0 : LDA E01E,Y     : A=80 X=FF Y=3A SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E009 : 99 FF FF : STA FFFF,Y     : A=80 X=FF Y=3A SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E00C : 88       : DEY            : A=80 X=FF Y=39 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00D : D0 F7    : BNE E006       : A=80 X=FF Y=39 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E006 : B9 1E E0 : LDA E01E,Y     : A=EF X=FF Y=39 SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E009 : 99 FF FF : STA FFFF,Y     : A=EF X=FF Y=39 SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E00C : 88       : DEY            : A=EF X=FF Y=38 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00D : D0 F7    : BNE E006       : A=EF X=FF Y=38 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E006 : B9 1E E0 : LDA E01E,Y     : A=10 X=FF Y=38 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E009 : 99 FF FF : STA FFFF,Y     : A=10 X=FF Y=38 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00C : 88       : DEY            : A=10 X=FF Y=37 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00D : D0 F7    : BNE E006       : A=10 X=FF Y=37 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E006 : B9 1E E0 : LDA E01E,Y     : A=01 X=FF Y=37 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E009 : 99 FF FF : STA FFFF,Y     : A=01 X=FF Y=37 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00C : 88       : DEY            : A=01 X=FF Y=36 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00D : D0 F7    : BNE E006       : A=01 X=FF Y=36 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E006 : B9 1E E0 : LDA E01E,Y     : A=E6 X=FF Y=36 SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E009 : 99 FF FF : STA FFFF,Y     : A=E6 X=FF Y=36 SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E00C : 88       : DEY            : A=E6 X=FF Y=35 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00D : D0 F7    : BNE E006       : A=E6 X=FF Y=35 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E006 : B9 1E E0 : LDA E01E,Y     : A=F3 X=FF Y=35 SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E009 : 99 FF FF : STA FFFF,Y     : A=F3 X=FF Y=35 SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E00C : 88       : DEY            : A=F3 X=FF Y=34 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00D : D0 F7    : BNE E006       : A=F3 X=FF Y=34 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E006 : B9 1E E0 : LDA E01E,Y     : A=D0 X=FF Y=34 SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E009 : 99 FF FF : STA FFFF,Y     : A=D0 X=FF Y=34 SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E00C : 88       : DEY            : A=D0 X=FF Y=33 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00D : D0 F7    : BNE E006       : A=D0 X=FF Y=33 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E006 : B9 1E E0 : LDA E01E,Y     : A=88 X=FF Y=33 SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E009 : 99 FF FF : STA FFFF,Y     : A=88 X=FF Y=33 SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E00C : 88       : DEY            : A=88 X=FF Y=32 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00D : D0 F7    : BNE E006       : A=88 X=FF Y=32 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E006 : B9 1E E0 : LDA E01E,Y     : A=09 X=FF Y=32 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E009 : 99 FF FF : STA FFFF,Y     : A=09 X=FF Y=32 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00C : 88       : DEY            : A=09 X=FF Y=31 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00D : D0 F7    : BNE E006       : A=09 X=FF Y=31 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E006 : B9 1E E0 : LDA E01E,Y     : A=D0 X=FF Y=31 SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E009 : 99 FF FF : STA FFFF,Y     : A=D0 X=FF Y=31 SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E00C : 88       : DEY            : A=D0 X=FF Y=30 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00D : D0 F7    : BNE E006       : A=D0 X=FF Y=30 SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E006 : B9 1E E0 : LDA E01E,Y     : A=00 X=FF Y=30 SP=FF N=0 V=? D=0 I=0 Z=1 C=?
E009 : 99 FF FF : STA FFFF,Y     : A=FF X=FF Y=30 SP=FF N=0 V=? D=0 I=0 Z=1 C=? prediction failed
E00C : 88       : DEY            : A=FF X=FF Y=2F SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00D : D0 F7    : BNE E006       : A=FF X=FF Y=2F SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E006 : B9 1E E0 : LDA E01E,Y     : A=D1 X=FF Y=2F SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E009 : 99 FF FF : STA FFFF,Y     : A=D1 X=FF Y=2F SP=FF N=1 V=? D=0 I=0 Z=0 C=?
E00C : 88       : DEY            : A=D1 X=FF Y=2E SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00D : D0 F7    : BNE E006       : A=D1 X=FF Y=2E SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E006 : B9 1E E0 : LDA E01E,Y     : A=01 X=FF Y=2E SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E009 : 99 FF FF : STA FFFF,Y     : A=DF X=FF Y=2E SP=FF N=0 V=? D=0 I=0 Z=0 C=? prediction failed
E00C : 88       : DEY            : A=DF X=FF Y=2D SP=FF N=0 V=? D=0 I=0 Z=0 C=?
E00D : D0 F7    : BNE E006       : A=DF X=FF Y=2D SP=FF N=0 V=? D=0 I=0 Z=0 C=?
... etc ...

Edit - I've investigated that further, and there were two problems there. One was that the logic analyser was sampling at a much lower rate than I was requesting - I don't know why. I turned up its sample rate to compensate, but coming back to it all later on I found that it wasn't running slow any more, so all of a sudden I had far too many captures, and I've turned that down again now in my command line, to 50kHz. My sketch is inserting at least 100us delay on each phase of the clock, and this leads to five or six samples being taken within each clock period, which feels like a good amount.

The more serious problem was that I was tapping the data bus of my computer on the far side of a transceiver, and the propagation delay of the transceiver was leading to my circuit sampling the data bus too early. Inserting two AHCT inverters between the CPU clock and my circuit delayed things enough to resolve that. Connecting it to the CPU's data bus directly also worked but I'd like to avoid adding load to that if possible.

I also had bugs to fix in my Arduino sketch code, and it's still pretty terrible code - I don't find Arduino code comfortable to write. I will revisit it another time though, and for now I'll draw a line under this, make a PCB and say it works.

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gfoot

Post subject: Re: Data bus logging at higher clock speeds

Posted: Fri Aug 11, 2023 9:24 am

Joined: Fri Jul 09, 2021 10:12 pm
Posts: 741

Having used this for a bit, I'm finding that 32K of SRAM is OK if you can trigger the capture at near enough the right moment, but is quite limiting. I designed the device to potentially support a second SRAM chip to double the capacity, so that is an option.

I can see good SMD static RAM in larger sizes, e.g. 128Kx8 or 16 bit.

However since I was looking at SPI EEPROMs and especially liking the fact that they can do serial reads and writes without requiring an address bus (no external counters), I looked up SPI SRAM options and there seemed to be some good ones, e.g. this kind of thing that actually supports 4-bit wide reads and writes at 20MHz:

Two of these in parallel would capture the whole data bus; a third could capture some control signals; and it would remove the need for all the external counter ICs. They're 1Mbit ICs and I'd be using 4 bits from each per sample, so that'd be 256K of samples in total.

It's not quite as fast as I'd like though, according to the datasheet. It is possible that another set of them could be used, alternating between them on successive clock cycles, to double the frequency. The overall memory size would then be 512K of samples. That seems like a lot of separate ICs, but I don't think it's unreasonable.

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