A question prompted by Garth's comment in the Newbie forum:And Jeff's linked topic "Managing the 65816 multiplexed bus".

Once PHI2 is brought low does the '816 not drive the data bus for the next 10ns after?

The datasheet would seem to say it does not as the the Read Data Hold Time runs 10ns into the new cycle. Jeff's topic agrees but is there a measurable answer?My own adventures show that the address bus is driven to the new address within about 10ns. So then does that imply the bank address driven onto the data bus in a similar time?

Cheers,
Andrew

I would expect the data and address outputs to be driven at pretty much the same time - if they have different loading then they may respond at different rates.

I think you know this, but note that "read data hold time" is the requirement on other chips, during a read cycle, not to change the logical value on the bus until 10ns after the clock falls. In practice, such chips will have a chip enable or output enable which will go low as a function of the address decoding and/or the clock, and may stop driving sooner or later than this. As a bus won't spontaneously change rapidly when no longer driven, what's usually the important point is that no other driver is enabled too soon after the clock falls.

Hi, Andrew. Figure 4-1 (which you included in your post) shows the last portion of one cycle and the entirety of the cycle that follows.

The third trace from the top illustrates data bus activity during read cycles. We see read data from the mobo's memory or IO, which we expect to cease driving soon after Phi2 falls. (But not too soon, as we'll see.) Shortly thereafter, the '816 begins driving, applying the Bank Address onto the bus.

The fourth trace from the top illustrates data bus activity during write cycles. We see write data from the '816; then, shortly after Phi2 falls, the '816 continues driving but a transition occurs, and eventually it is a valid Bank Address that appears.


You've annotated the read data trace, and yet your question asks about the '816 driving. For a read cycle, the '816 doesn't drive data on the bus; the mobo does! So, I'm not sure I understand the question.

The mobo is expected to maintain read data on the bus for at least 10 ns after Phi2 falls; that's what the tDHR spec is expressing. Hope this helps,

-- Jeff

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That's what got me thinking; I thought I didn't respect tDHR and just and disabled the SRAMs /OE by NANDing RWB and PHI2 together. I didn't. I did something worse. I left the SRAM /OE active the entire time RWB was high (with /CS tied to GND). Ouch.

Yup, that's my question. During a read does the '816 drive the bank address onto the data pins immediately after tDHR (even if it's the old BA from the previous cycle). Or do the data pins stay high impedance (from the read) until the BA is valid?

Reflecting after typing this out it must be the second. Why would WDC put effort into driving the 'garbage' onto the data pins after a read and then later change that to the correct BA? They wouldn't, they'd just be causing a potential bus collision for a reason that only exists in my own head.

Thanks for the replies! You've cleared up my thoughts.