Hi guys

I'm looking at my 6502GPD-D design and what can be improved to get a faster and less noisy design. The design so far runs ok at 16MHz, but 18MHz or higher is unreliable-to-not usable.
So far I'm looking at possibly adding serial to it (rather than relying on a card) and a few other things with regards functionality.
However, at the moment I'm looking at layout and PCB layer stack up.
Stack up wise, I've been doing a little research and 4 layers is less than optimal (although it does work, obviously).
I was thinking of going to 6 layers with the following:
1: SIG
2: GND
3: PWR
4: PWR
5: GND
6: SIG
Then using plenty of large vias to connect the two ground planes together, along with putting in vias near signals running to ground. This means that return paths are improved and radiate less.
I did think about converting layer 4 into SIG (signal) as well, but I want to keep power planes as close to each signal layer as possible.

What does everyone think? Is this overkill for a 65C02?

Also, does any one have any recommendations component placement? I'm, looking at dropping the clock generation cirtcuit down a little and moving the RAM/ROM down and to the left towards the slots, making for shorter bus traces.
In addition, I was possibly looking at moving the CPLD and MPU (65C02) from below the slots to the left instead. The Address and Data bus headers will be moved in closer to the RAM/ROM ICs as well.

Am I barking up the wrong tree on this?

See attached file for a layout.

[edit to clear up some confusion: It's been pointed out below that the PCB refers to slower 55ns RAM, but just to advise that I'm actually using 12ns AS7C4096A SRAM via an adapter]

If I was going for speed, I'd put the CPU and RAM close together along with the clock and CPLD, and keep peripherals and expansion slots on a slow bus on the other side of a transceiver perhaps (or maybe the CPLD can be the glue there too). The idea is to allow the critical components to work together in as ideal an arrangement at possible, to achieve the fastest possible speed for general processing, and use wait states (e.g. clock stretching) to slow things down for infrequent I/O operations. I'd also consider copying the ROM to RAM on startup over the slow bus, to keep the fast bus as unencumbered as possible.

This was broadly my plan for a modular system where the CPU board would contain pretty much just those components I mentioned above, and most operations stay within that board, which can also comfortably be quite small and cheap to produce. Everything else (probably including ROM) would be on other boards.

I'm not sure what the benefit would be of having multiple ground and power planes in your case. I'd have thought one dedicated plane of each would be fine.

6 layers does seem overkill for a 65C02 SBC, if you consider that my 65816 SBC is a 4 layer board (not even manually routed) and it runs fine at 20MHz.
the PCB i made for it is also one of the most compact i've made so far. it's 10x10cm and it's packed with compoenents.

so i think keeping traces short and pushing your components closer together will already give you some good results.
plus i would start to move away from parallel expansion slots that are directly connected to the System bus, as it just slows things down. (for example if i insert my Video Card into my SBC it won't run at 20MHz anymore)

i would just rely on something serial like SPI (maybe implemented in hardware the CPLD). hardware SPI is fast enough for basically anything you could want to connect, except video and audio maybe.
if you do want to keep atleast 1 parallel connector for some high speed device like a video card, maybe put it behind some buffers that are only enabled when the card is accessed.

also consider using some faster RAM, a fast clock won't do anything if you're slowing the CPU down every bus cycle.
the AS6C4008-55 is a 55ns chip. so consider using the IS61C5128AL-10, which is a 10ns chip with the same capacity 512kB, and it's usually cheaper as well.
you will still need wait states for the ROM (though the VIA and whatever you'll throw into the CPLD should be fast enough), but that shouldn't be an issue if you only use the ROM to bootload code into RAM (or copy itself into RAM before disabling the ROM).

Thanks for replying, guys.
Just to note that I'm using faster RAM - it was original build for AS6C4008 memory, but I now use 12ns AS7C4096A SRAM using an SOJ to DIP adapter (I should have said).
The CPLD slows the system down when accessing the ROM, but runs at full speed when accessing the RAM. Also, I am planning to copy ROM to RAM.

With regards the GND planes. distance between the signals and the ground planes is something of an issue, but this is more of an issue with higher speeds. I think this might not include something like 14-20MHz, which is really why I'm asking.
The reason I had the slots on the main busses was really for something like a video card, but perhaps (as suggested) I could move two off for slower buffered access and keep one for video?

I would buffer the video port as well, with a transceiver near the CPU. If it's write-only then bus speed doesn't matter much - the 6502 will struggle to send more than one byte every four or five cycles anyway. Especially for read operations you may have to tolerate a slower clock even if its directly connected, as the signals have a long way to go - so you might as well separate that off and avoid bogging down the main bus with driving those long off-board traces.

Are the peripherals going to be connected by ribbon cables or directly attached? It may be wise to alternate all the signal pins with ground or power pins if you're using cables.

The peripherals are edge card connected only. I.e. PCB to PCB.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Probably the biggest single improvement you can make is to get rid of the adapter and alter your PCB so it'll directly accept the SOJ package. This'll take some work, but not that much, and it'll provide a lot more benefit than changing from 4-layer to 6-layer.

That's because the DIP pinout is a relic from the slow, old days. It features only a single Vcc pin and a single Gnd pin. You'll notice that more modern RAMs feature two significant changes: multiple Vcc and Gnd pins, and moreover they're located centrally (rather than at the corner of the package).

Also, I second George's suggestions, especially putting the CPU and RAM close together along with the clock and CPLD.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Hi garth

Many thanks. I'll have a reread as it's been a number of years since I read your guides/tutorials and I think some of it's been possibly been updated since (and my memory isn't as good as it once was!). I'm going to go through the videos over the next few days. With regards point #4: my connectors do have grounds dotted up and down and some VCCs (not as many as I would like!) - also, they are set so reverse connection isn't super bad. I learned that from you a while ago .
I didn't realise the distance between the two middle layers of a 6 layer baord was so small - so having 2 VCC plains seems pointless in retrospect. However, I thought 2 ground plains might be the main benefit. Maybe not worth the cost of a 6 layer PCB though. What I might do is go for a 1.2mm 4 layer instead.
Anyhoo, going to watch those videos and have a reread. Cheers!

I had wondered (but clearly not long enough) as to why they had started introducing more power rail related pins. Good to know.
I use DIPs becasue it's just so much easier to swap out a duff part - but perhaps I should revisit that. Can I get away with having a custom DIP pinout reflecting all of the pins on the AS7C4096A? Or would it still not be quite good enough and I have to directly solder?

Ok, so far here's what I'm looking at. It is quite subject to change given the comments in this thread and also what I mean hear/see in those link Garth has kindly provided:

- Main bus ICs as close together as humanly possible
- Keep 'moslo' clock stretch circuit for ROM access, copy ROM to RAM on boot (already implemented, but will keep)
- SOJ package SRAM soldered directly to the PCB -or- on custom DIP adapter reflecting the pinnout of the IC, including power - see previous post.
- Move slots off main bus. Put behind buffers or VIAs? I prefer buffers. Would this be good enough? I'll reread Garth's posts.
- 1 bank of 16KB dual port ram will connect to main buses, but the port B to a slot. Any issues with this?
- Signal vias to have ground vias next to them for return paths
- 4 layer PCB 1.2mm. Stackup: SIG GND PWR SIG

I'm going to have to reroute the buses. Is crying permitted?

Having done a number of 6502 overclocking experiments into 30+ Mhz, I believe you need to simplify your design, reduce component count, reduce wiring length and signal loads and put them all in a small pc board. All my overclock boards are either 2-layer pcb or hand-wired prototype boards (no groun/Vcc planes); the key is small board and short connections.
Bill

Edit, this is my most recent overclocking experiment, viewtopic.php?f=4&t=7433. I was shooting for a 40Mhz DOS/65 computer, but that requires supply voltage of 5.4V. 36Mhz is probably the limit for nominal voltage

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I'm impressed that you keep it up to date and it's a great source of information for the less knowledgeable (such as me). My condolences with regards your mother-in-law.

SOJ sockets are a thing! So, the AS7C4096A doesn't need to be soldered in place... although there are advantages to having it so.

You mean create a new, improved adapter, whose DIP side has some extra pins connecting to the mobo? To make a significant difference, the changes would result in something of a monstrosity, I'm afraid. But if you haven't already, do be sure to mount two bypass caps on the adapter itself, one on each side of the SOJ IC and very close to it. That's if you decide to keep using the adapter. And if you ever swap out the adapter and insert an actual DIP ram, you might be forced to drop the clock speed. After all, it's the actual silicon die we need to connect to... and, on a DIP package, the (single, not multiple) Vcc and Gnd pins are each about an inch away from the die, and there's nothing that can be done about that.

If maximum clock rate is the goal, I'd seriously consider starting over. Begin by laying out a tight RAM/CPU/CPLD core, then then arrange Everything Else (including ROM) around it... ideally separated from the core by buffer ICs or at least damping resistors, and running with a wait-state. (And for the latter I'd maybe lean toward using the CPU's RDY input. A comparison of that technique vs. clockstretching can be found here.)

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html