Barnacle wrote:
I wonder if you're simply isolating the oscillator from the rest of the counter by powering it this way? It would definitely be interesting to see the Vcc signal - you'd probably need to trigger the scope from the divided output to see if any noise on it is correlated.
Circuit #1:
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Circuit #2:
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That was a good idea, Niel. Could this noise actually be cross-talk from the `163's outputs, and not ground bounce or VCC noise generated by the oscillator? The spikes correlate with the oscillator's pulses, as expected, but they're bigger when more of the `163s outputs are switching at the same time.
Maybe it's worth reiterating that both these circuits work. Even the biggest spikes are not in danger of creating logic errors. However, AN-375 from my National Semiconductor HCMOS data book says that,
as a good rule of thumb, it's generally good design practice to restrict both Vcc and ground noise to less than 250 mV. Since this counter is going to be clocking a pretty touchy and (for me) complex circuit, I'd like to get it as clean as possible. Is there some way to get the effect of circuit #1 without feeding the `163 through the wrong pin (and without the almost 1v drop)? My first thought would be just to send the outputs through a 74HC14 a couple of times. Anything better than that spring to mind?
cjs wrote:
Paganini wrote:
The four floating pins are the parallel load pins for the counting register. They're disabled when the load pin is held high and are not causing any problems.
I am pretty sure I am missing a lot in this thread, but are you really sure that they're not causing any problems?
BigDumbDinosaur wrote:
You sure about that?
Yes, I'm sure!
OK, though, BDD is right; "disabled" was an overstatement. The pins are not tri-stated. *However.* No less a visionary than Radical Brad left those inputs floating in Vulcan 74. gfoot himself (Hi George! Thanks for posting to the thread!) left them floating in his prototype of this selfsame circuit. That picture is still the cover flow photo of the project's Hackaday page! I'm not going to argue with anyone who says it's good practice to terminate CMOS inputs, or that leaving them floating is a bad habit. I, too, have accidentally powered a logic gate without connecting its VCC. But when I say that these four particular inputs are not causing any problems I mean that these four particular inputs are *in fact* not causing any problems, not that I assume they aren't, or believe they aren't. I know that they aren't because:
1. Logically, they shouldn't be.
2. Prototypes for much larger and less forgiving projects by designers whose works I admire and study leave them floating without issue.
3. The floating pins are common to both circuits #1 and #2 and are therefore not responsible for the difference in behavior between the two circuits.
4. I checked!
C'mon guys! Since the point of isolating two ICs out of a much larger VGA circuit is to investigate how they respond to different conditions, and because tying off four pins is trivial, of course I've tied them to both VCC and to GND in both circuits while watching the scope. Those jumpers went away along with all the bypass caps into the category of "things that don't make a difference" before I took the breadboard photo, because I was trying to make it *visually simple* in order to focus on one variable: the difference in VCC wiring.
So BDD can relax:
BigDumbDinosaur wrote:
Quit being stubborn and terminate those inputs!
They're terminated on my schematic, they're terminated on the full circuit on my big breadboard, and they've even been terminated every which way on the 2 IC isolated circuit.
TI Data Sheet wrote:
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Interesting, I just read that data sheet two days ago, and mine has no such note. Then again, mine is copyright 1982 even though the data book is from 1988, so...