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I was just getting started here and it is easy to see, yes,
there are 4 address pins "free" on the ISA buss compared to the 6502 available memory.
so, what to do with them?

I am of a mind to use them as 'chip select' or 'bank select' and I am ok to burn a few clock cycles to change 'upper address bits with a 4 bit register' and have 16 times the normal ram. or address space. context switching, dedicated devices etc.

[*]leave unused
[*]bank or device switching
[*]use a delayed read/write operation to use an external register for the extra bits

I have Intel ISA Spec 2.01 Sep 89, It does say a Maximum of 1MB. (section 6.1)
In several other places it says, 8 bit cards use 64K, (section 6.2) and in other places (add on card focus) that only 10 address lines are used traditionally.
ISA was intended by Intel to use their 8259A, and so unless we try to implement that exactly, we are going to diverge a little.
in 6.3 and further it says that data is moved in 8 or 16 bit transfers.
I think "using ISA" for a 6502 is probably a worthy experiment.

The primary goal here in not necessarily to use the physical ISA hardware, though that is highly appealing as it is off-the-shelf components. PC/104 and PCMCIA however are both built on top of ISA and getting it established is for the moment, as good of a buss to use as any, primarily due to future connectivity with existing standards.

so what other thoughts are there on a 6502 using an ISA physical connector or design specification (since they exist and it is well documented). a 65816 is clearly more suited to this as Rob Finch has developed such a system. what caveats and considerations are there for the ISA bus?

well you likely don't want to connect all 16 CPU address lines to the bus as that would fill the entire address space with ISA, leaving nothing for RAM, ROM, or dedicated IO.
that's why i suggested a smaller window so you can still use the rest of the system normally without having to use ISA Cards to get some RAM/ROM (though that would also be an option).
if you only connect A0-11 from the CPU it would give you a 4k window, and the remaining 8 address lines (A12-19) could be controlled from a VIA or similar IO register.
and that also ignores the fact that you have to generate the IOR/IOW and MEMR/MEMW signals, which would likely be handled by some decoing logic. plus some wait state logic since i doubt ISA Cards would work at +10MHz without any wait states.
there is also the issue of seperate IO and Memory Access. you could do it with another pin from a VIA, or with a CPU Address pin.
so your 4k window would be mirrored in memory, accessing one would count as an "IO" access and the other as "Memory". though using the VIA would save you 4k of memory.

another small problem is the BIOS ROM that some cards have on them, which usually contain code and data to initialize and use the card. of course x86 assembly won't run a 65C02, which either means avoiding such cards or disassembling the ROM and replicating it's function in 6502 assembly.
the second option could be kinda automated if you have some form of storage device. since you could have the CPU scan the ISA bus for any ROMs that might have matching 6502 replacements which could be loaded from storage.

either way i'd be interested to see how this could perform. being able to use ISA Cards would be pretty damn cool.

certainly.

http://www.6502.org/users/mycorner/6502 ... sa/isa.png

a lot of what I am doing is echoed by lee davison, echoed here on 6502.org

http://www.6502.org/users/mycorner/6502/suprchips/isa/

he just tied the top 4 pins to ground...

I will stick with it as I go.

I am thinking of using a board controller to hand a lot of this off to,

in simple terms, I think a latch (and Im guessing a driver) could hold the chip select/enable bits, and upper 4 address bits, mapped to a vector/memory location, so on the next cycle it would fill in the top byte

to me, this makes sense if you set them, do a lot of stuff, and change them again and use zero page and stack to move between upper and lower ranges.
if, they get used at all, I think a basic on this board, on expansion board, somewhere on a cable, or maybe different speed protocols, idk yey, accessing those upper 4 bits, it really just an 'extra' for later, plenty with 16 bits as is