In the PCI specification available here:

https://www.ics.uci.edu/~harris/ics216/pci/PCI_22.pdf

which is 2.2, it says on page 127 of the spec (and page 147 of the PDF) that the Maximum Cycle time is "Infinity".
It also says in Note 1, that: "all PCI components must work with any clock frequency between nominal DC and 33 MHz."

I just want to double check here then that this means the same thing as "Static" and that you can run at any speed you want below 33Mhz, including single stepping?
(It says PCI is inherently CMOS technology somewhere.)

While PCI is a 32-bit bus, you can use 16-bits of it empty or use for other addressing data etc, or send two-words at a time out and need two read ops to receive. That is not the important thing, its that, is this correct, you can slow PCI down to whatever speed you want, 24Mhz, 12 Mh, 6 Mhz, 9600 baud, held static?
Is that what I am reading there?

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

that is an interesting idea.

there are still loads of cheap PCI cards available, and the connectors are technically through-hole parts so it shouldn't be hard to solder them.
but i think the main issue would be the software overhead. (not even including the actual interface).
because by the time PCI came around CPUs were way more powerful and expansion devices became pretty complex in their command sets and such.
you would likely have to scour the internet for a datasheet for the card/controller IC on it to write your own driver from scratch, or hope that someone reverse engineered some existing driver, or there is just source code for it available that you can use as a base.
and by the time you actually have something running, what would the bandwidth be like? like, could you actually keep a graphics/sound/ethernet/etc. card fed with data and then still have time for actual processing?

this seems like a scenario where having a second processor specifically for IO seems like a good idea.

That's what I was thinking, thanks!
It is also covered here in the PCI Mobile Design Guide
http://www.drydkim.com/MyDocuments/PCI% ... /mdg11.pdf

It is covered a few places and discussed on Page 13, and repeatedly throughout the document.
Ill check the PCI 2.2 again, the MDG says motherboards can set any clock speed from DC to 33MHz and lockout buspeed changes (you can change PCI bus speed on the fly if its 'inert' at the time)

Not that 8 and 16 bit cpu need a 32 bit bus, it is there if we want it. the 65816 has 24bit addressing, that leaves 8 extra bits for MMIO devices on top of the existing PCI device bus/id/function channels...

so, RAM banking and lots of peripherals is super easy, the 65816 or 6502 (if I do get them working) can certainly find a way to make use of the extra lines somewhere, or just ground them out if not needed.

I myself am going to start with a 6502 on an ISA, then a 65816 on big-ISA, and go from there.

I am fairly certain, 65816 can sit nicely on a PC/104+ system and uh, 'work okay'.




I am looking at PC-Card myself for portable devices and PC/104(+) for desktop stuff.
These are basically ISA/PCI, or built on top of them. Didn't you do a 6502 to CF card or was that someone else? its really similar too.
The videos I am watching and the specs I am reading seem like the PCI is controller by signals and a host controller or whatever does a lot of the lifting. Ti makes the 1520 and there are other PCI chipsets out there.

For my designs, the CPU (6502/65816/etc) is a logic unit, and a dedicated board controller handles I/O and interrupts wherever possible so the CPU can CPU. I am planning to use a PIC24 atm, as its matches the 65816 well im(novice)o. I may look at existing available PCI Host controllers and see if they can supplant the PIC, however I think we now moving into true North Bridge South Bridge territory, with the PIC and PCI chips in each role.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

maybe, I am more interested in PCMCIA and such for peripherals.
part of the trouble with throughput will be mitigated by the bus running at much less than 33Mhz.
its a ways off, for now, ISA looks like a good fit for 6502/65816, and might be worth trying to adhere to.
Ill continue to post results once I get them.

I really am interested in running two CPU as if they were just 'twice as wide',
for the I/O controller, I'll probably use a PCI host chip or a PIC microcontroller