10) Control register




;---

Please don't get confused:
It was a bit difficult for me to spot what goes where in the silicon,
so I just took the lump which contained Command register Bit 0
and Control register Bit 0, and did a schematic for both.

The Control register just uses one half_static transparent latch per Bit,
latches are controlled by high_active register write control signal W$3
(plus low_active signal W$3#).

W$3 and W$3# are generated in "6) address decoder".

Latches are cleared with RES=HIGH during a hardware reset.

The inverted and non_inverted outputs of the Control register Bit latches
go into "12) Control/Command register output decoding".

11) Command register




;---

The circuitry of the Command register Bits is a bit unusual.

Basically, for every Command register Bit we have a master/slave flipflop
which is built from two half_static transparent latches.
;
The hold path of the first latch is the unusual part,
and I think that it was build this way to save some space on the chip.

The outputs of the Command register Bits change with the falling edge of W$2,
after the CPU has completed the register write.

The first latch is controlled by W$2 (and W$2D#).
The second latch is controlled by W$2# (and W$2).

W$2, W$2# and W$2D# are generated in "6) address decoder".

The W$2D# falling edge happens together with the W$2# falling edge,
but compared to W$2# the W$2D# rising edge is delayed by two logic gates.
I think that's for compensating the propagation delay of the second latch,
which feeds the hold path of the first latch.

All Command register Bits are cleared when RES=HIGH during a hardware reset.

Also, Command register Bit 4..0 are cleared by W$1,
that's the programmed reset when the CPU writes the Status register.

Be warned:
The effect of a programmed reset on the Command register is different
for different implementations of the 6551.
;
For instance:
MOS 8551: programmed reset clears Command register Bits 4,3,2,1,0.
MOS 6551: programmed reset clears Command register Bits 4,3,2,0, but sets Command register Bit 1.

The inverted and non_inverted outputs of the Command register Bits
go into "12) Control/Command register output decoding".

12) Control/Command register output decoding tapeworm

The low_active and high_active outputs of "10) Control register"
and "11) Command register" go into a lump of conventional logic,
which buffers some of the register outputs,
and decodes combinations of certain register Bits.

The best way of dealing with a lump of conventional logic
is to number the transistors in the silicon and in your schematic,
else it would become very difficult to correct errors by tracking them back.

The outputs of "12)" go to different parts of the chip,
but most notably into "14) RX control" and "17) TX control".

Please note the two signals which go into "12)" from "17) TX control":
TX_SR_NE is HIGH, when the TX shift register is not empty.
TX_BRK_ACTIVE is HIGH, when the transmitter transmits a BRK.
;
TX_SR_NE and TX_BRK_ACTIVE disable some of the decoded outputs.

13) Baud rate generator

When using no external clock source (plus an external predivider),
signal XCLK is supposed to be 1.4832MHz,
and it's generated by "1a) XTAL clock generator" //plus an external crystal.

XCLK goes into a RS flipflop in inverted and non_inverted form.
Said RS flipflop generates the internal clock signals for the Baud rate generator.

Control register Bits 3..0 (in low_active and high_active form)
control a lookup table (ROM), which feeds the data inputs of a
11 Bit binary up counter.

Note:
For Bit 10..4, the lookup table has high_active outputs.
For Bit 3..0, the lookup table has low_active outputs.
That's a nice trick for saving some chip space. //But it adds to the confusion.

The counter uses a carry lookahead mechanism in three steps:
Bit 0..3, Bit 4..7, Bit 8..10.

The carry chain uses the usual low_active/high_active carry scheme.
The counter circuitry isn't much different from what we had seen in other MOS chips,
except that it's the most compact/dense counter layout I have ever seen so far.
Note that the data inputs/outputs of the counter Bits also have low_active/high_active form,
what sure adds to the confusion.
//Because you can't tell at first sight whether the outputs of the lookup table are high_active or low_active.

After the counter has reached terminal count, that's $7FF,
instead of rolling over to $000 it is getting reloaded with the value from the lookup table.
The carry output of the counter triggers at twice the Baud rate.

The counter output carry flips a master/slave flipflop by using an XOR gate.
The flipflop is built from dynamic transparent latches.

;...

Now for the less obvious part:
The two 2:1 multiplexers which are used for switching clock signals.

During our 6509 dissection, we had seen a trick for building a 2:1 multiplexer
which has one inverting data input by using an AND gate plus two NOR gates.
8551 uses this trick in the Baud Rate generator, too.

TX_CLK16# is 16* TX clock, it goes into "19) TX div16", the TX clock predivider.

A 2:1 multiplexer either feeds TX_CLK16# with the master/slave flipflop
which toggles with the counter carry, when CTL3..0 is different from $0.
;
Or if CTL3..0 is $0, it feeds RX_CLK16# with the output of the RS flipflop
which is running at XTAL speed. //external predivider required.

Note:
When CTL3..0 is $0, the counter does not reload from the lookup table at terminal count,
but rolls over to $000 while still counting.
And the lookup table defaults to the counter input value for 3600 Baud.

Another 2:1 multiplexer with an inverter attached to its output generates RX_CLK16,
which is 16* RX clock and goes into "18) RX div16", the RX clock predivider.
;
Depending on CTL_4#, RC_CLK16 either is fed with:
CTL4=0: signal from the RxC pad //see "4a) RxC"
CTL4=1: inverted TX_CLK16#

14) RX control

Guys... I'm just a lone old hobbyist who is supposed to have a job and a life.
Figuring out how that thing works in detail goes beyond my capacity.
Be happy, that I "somehow" was able to just sort/identify the parts and to guess what goes where.

If anybody figures out how that thing works in detail, and writes a technical article about it,
I would gladly link to it here... as long as I am still alive... so you better try to get this done before 2038 or so.

;---

What I had labeled "RX control" is a big lump of random logic.

High_active signal RX_TC, generated in "15) RX Bitcounter", goes HIGH
if said RX Bitcounter is convinced to have all the data Bits of a frame received.

RX_CLK# is the low_active receiver clock (running at Baud rate),
it is generated in "18) RX div16", the RX CLK predivider.

When RX_TC goes HIGH, we have an edge detector, which generates a LOW pulse
on signal RX_CLK_FE# at the rising edge of RX_CLK# (RX CLK falling edge).
RX_CLK_FE# is the clock signal for a sequencer.

;---

The sequencer is built from RS flipflops,
and it decides what to do with the Bits of a frame which follow the data Bits.
//Old school German PLC coders maybe would refer to that sort sequencer as "Schrittkette".
The RS flipflops somewhat default to "hey, something needs to be done" when RX_TC becomes active,
but again: priority of R,S inputs to Q,/Q outputs of them RS flipflops matters a lot, take care.

Then we have the trigger circuitry, which is supposed to detect that a Startbit is present.
To me, it looks like said trigger circuitry detects when a Startbit is _not_ present, and that's a difference.

Have you ever tried to figure out how the trigger/sweep circuitry inside an oscilloscope
which was built in the 80s actually works in detail ?
Spending 3 days+ with just trying to get smart of a few logic gates plus a flipflop and such ?
This here is worse.

Vieved from afar, to me it somehow almost looks like a Godzilla sized JK master/slave flipflop
which had spent too much time near Tschernobyl... but I could be wrong.

Anyhow: something related to "15) RX Bitcounter":
High_active signal RX_R seems to lock the RX Bitcounter into RX_TC condition.
High_active signal RX_S loads the RX Bitcounter "with the number of Bits to be counted".

I assume that RX_S goes active after/when there was a Startbit.

;---

RX Parity calculation is a bit tricky, but easy to understand.

It would have required the use of a master_slave flipflop built from two transparent latches...
...but the designers had just used one transparent latch plus a time delay instead,
just for saving some space on the chip.

;---

We have a transparent latch, which basically holds what went in at the RXD pad
for echo mode.

And we have another transparent latch which checks for frame error
by checking if there was something different than a Stopbit on the RX pad in a given moment...
I think it's the first Stopbit when there is more than one Stopbit.

;---

That's all, good luck.

15) RX Bitcounter

Shift register is built from master/slave flipflops,
each master/slave flipflop contains two half_static latches.
...Again.

When ignoring the hold paths of the latches,
what we have is a 4 Bit shift register which works as a ring counter.

We have a RS flipflop, which generates the clock signals for the shift register from RX_CLK#.
Note, that clock generation for the counter stops when the counter has reached terminal count,
what is indicated by high_active signal RX_TC going HIGH.

Clock signals are:
RxPHI1 (and inverted RxPHI1N),
RxPHI2 (and inverted RxPHI2N).
Note, that these clock signals also control "8)" RX shift register.

High_active signal RX_S asynchronously loads the counter with L7#, L6#, L5#,
selecting the count for 6..8 Bit data length.

High_active signal RX_R pushes the counter toward terminal count.
Note, that we have another RS flipflop which technically is part of the ring counter.

RX_S and RX_R are generated in "14) RX control".

16) TX Bitcounter

Shift register is built from master/slave flipflops,
each master/slave flipflop contains two half_static latches.
...Again.

When ignoring the hold path of the latches,
the circuitry looks pretty similar to what we had in "16) RX Bitcounter".

Except that clock generation for the counter doesn't stop
when the counter has reached terminal count.

17) TX control

Like "14) RX control", it's quite a lump of random logic.
Just a bit bigger, but better to understand.

//If anybody figures out how that thing works in detail, and writes a technical article about it,
//I would gladly link to it here...

;---

High_active signal TX_TC, generated in "16) RX Bitcounter", goes HIGH
if said TX Bitcounter is convinced to have all the data Bits of a frame transmitted.

TxPHI0 is the high_active transmitter clock (running at Baud rate),
it is generated in "19) TX div16", the TX CLK predivider.

When TX_TC goes HIGH, we have an edge detector, which generates a LOW pulse
on signal TX_PHI0_FE# at the falling edge of TxPHI0.
TX_CLK_FE# is the clock signal for a sequencer.

;---

The sequencer is built from RS flipflops,
and it decides what to do with the Bits of a frame which follow the data Bits.
//Old school German PLC coders would identify that sort sequencer as "Schrittkette".

;---

TX Parity calculation works pretty similar to the RX Parity calculation we had in "14) RX control".

It would have required the use of a master_slave flipflop built from two transparent latches...
...but again the designers had just used one transparent latch plus a time delay instead,
just for saving some space on the chip.

;---

We have a half_static transparent latch, which buffers the output data.

The OR gate at the data input of the latch might look a little bit confusing at first sight,
the trick is that the inputs of the OR gate (which are low_active signals) default to LOW.

The output of the latch goes into a three input NOR gate,
which gives out the high_active TXDout TX data.
It goes into the driver of the TXD pad, see "4c) TXD, CTS#".



//sorry for the ZIP, but there appears to be a limit to the size of PNG files here in this forum.

18) RX div16 //RX CLK predivider

Shift registers are built from master/slave flipflops,
each master/slave flipflop contains two half_static latches.
...Again.

After ignoring the hold path of the latches,
what we have basically are two 2 Bit ring counters (shift registers)
plus one RS flipflop per counter for generating the counter clock signals.

The first ring counter always divides by 4.
The second ring counter divides by 4 or by 2 (for supporting 1.5 Stopbits).

And that part with the 1.5 Stopbits it what makes detection of terminal count
a bit more difficult.

The first ring counter provides the clock for the second ring counter.
So that the ring counters either divide by 4*4=16 or by 4*2=8.

Note the falling edge detector, which tells "7b) Status register, Bit 3"
with a HIGH pulse on signal RX_CLK1_FEP that data is supposed to have
moved into the RX data register.

19) TX div16 // TX CLK predivider

Shift registers are built from master/slave flipflops,
each master/slave flipflop contains two half_static latches.
...Again.

After ignoring the hold path of the latches,
what we have basically are two 2 Bit ring counters (shift registers)
plus one RS flipflop per counter for generating the counter clock signals.

The circuitry is a bit similar to what we had in "18) RX div16".
Except that terminal count detection is a bit more simple,
because supporting 1.5 Stopbits is done by actively controlling the second ring counter.

I need to know, what them MOS chip designers had smoked.
I want the same.

That's all for now,
Amiga 8364R7 Paula is next.

Fantastic work! Excellent that you share your findings.

A real lesson, I think, that a UART is a very difficult design problem. I'm thinking it's almost the most valuable MSI chip you could make (or buy) - every other part of the system is in principle implementable in logic, and understandable as a synchronous system. But here, we have three clock domains (I think) and some very subtle and complex requirements.

It is just a little baffling that CTS is such a severe control signal.

Dieter, congratulations to you and your collaborators on another expansive exploration! The level and amount of detail you've addressed is amazing!

Speaking of detail, my attention this morning happened to land on the very intriguing oscillator discussion. I'll need a second cup of coffee before I try to fully absorb some of that content, such as Andrew's negative resistance observations in this post.

( And BTW not only intriguing but also amusing! Besides palpable truth, there's also plenty of wry humor in some of your remarks: )

Anyway, still speaking of detail, allow me to contribute one small observation of my own. And it's nothing profound; merely a fragment of humble, first-cup-of-coffee stuff.



Staring at the picture provoked me to redraw the Butler oscillator, as the original illustration "does not compute" for me. Notice that I've reversed the positions of V1 and V2.What's revealed is that the Butler Oscillator lacks the symmetry seen in the other two examples. Instead of two more or less identical sections which are cross-coupled, we have two amplifiers, one which produces voltage gain and one which does not (apparently just a buffer to provide low impedance output).

The matter is perhaps slightly OT, but, having redrawn the Butler to satisfy my own curiosity, I thought the result might be worth sharing in case others are scratching their heads just as I did. I find that the way a circuit is drawn can drastically affect its intelligibility. ETA: but who knows; perhaps some of you will prefer the original version!

Congratulations again, and thanks for the stupendous effort you've put into all of this,

Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Ed and Jeff, thanks for the kind words and the appreciation.

Them chip dissections are quite labour intensive,
and there is some circuitry in the 8551 I never have seen before.

But at least now everybody has a list of what to do with the 6551 handshake and XTAL pins.

;---

Jeff, it really is like this with amplifiers and oscillators...
...and how the one unintentionally could end up as the other.

If the teacher doesn't tell you about that at school in engineering classes, try to get your money back.


See, I had spent some days whith searching the internet for oscillator circuits similar to what's in the 8551.
I found nothing similar, I also found no radio amateur who had seen something similar.

The transistors and the "Collector" resistors almost are wired up like in an astable multivibrator.
On the other hand, the crystal and the "Emitter" resistors are wired up like in a Butler oscillator.

To me, it somehow feels like the astable multivibrator and the Butler oscillator had an illegitime spawn.
But that's what's in the 8551 silicon.

Oh yes, of course! -- you're right, it very definitely is!

I didn't mean to suggest you were joking. But your delivery is still humorous, and I enjoyed that!



-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html