Previous thread: 5719 dissection //Amiga GARY, CMOS gate array.

First: thanks to all those who make these chip dissections possible.

This thread is about a transistor level dissection of the MOS 8551 ACIA (Asynchronous Communications Interface Adapter),
brought to you by Frank Wolf and ttlworks, with a short cameo appearance of Andrew Holme.

The 8551 is the HMOS-II implementation of the 6551.
6551 was used in the Commodore PET, 8551 was used in the Commodore Plus/4.
There were peripheral cards with 6551 for C64, C128 and Apple II.

Since we were unable to find an 8551 datasheet in the internet:

The 6551 is a UART (Universal asynchronous receiver-transmitter)
for implementing RS232 serial communication.

With a 1.8432MHz crystal tied to the XTAL1\XTAL2 pins of the Baud rate generator oscillator,
it supports 15 Baud rates ranging from 50 Baud to 19200 Baud (19.2kBaud).
Higher Baud rates might be possible when using an external clock instead of the 1.8432MHz crystal.

Data Bits: 5..8, Parity: even/odd/none/SPACE/MARK, Stopbits: 1/1.5/2 (depending on the amount of Data Bits).

Unlike modern UARTs, 6551 has no FIFO, but only a one Byte buffer instead.
Means that at 19200-8-N-1, your CPU might have ca. 520µs of time "to do something" with the received Byte.
(19200-8-N-1 means: Startbit, 8 Data Bits, no Parity, 1 Stopbit. That's 10 Bits. At 19.2kBaud, one Bit takes 1s/19200=52.08µs)
;
If you are scrolling a 40*25 screen of text by software with a 1MHz 6502 while interpreting ANSI escape sequences,
you better be aware of this.

;---

Unfortunately, we were unable to find an 8551 datasheet in the internet.
We don't know what changes/bugfixes MOS had done for the different 6551/8551 revisions,
and we also don't know what changes/bugfixes MOS had done when switching from the 6551 to the 8551.

8551R2 (revision 2) is supposed to be the last version that MOS\CSG\Commodore had in production.

Rockwell was a second source manufacturer for the NMOS 6551.

Later, second source manufacturers for the CMOS 6551 included Rockwell (R65C51) and Harris (CDP65C51).
WDC still manufactures the CMOS W65C51.

Be aware, that there are little differences between these chips:
Hardware or programmed reset might have a different effect the Bits in the Command register,
and the crystal oscillator circuitry might be different.

//For practical use of the chip, I think it might be a good idea to permanently tie the CTS# pin to GND.

Datasheets:

NMOS:
MOS 6551, Dec. 1980.
Rockwell R6551, Jan. 1981.

CMOS:
Rockwell R65C51, 1989, page 6-185 (PDF page 1016) //flow control explained.
WDC W65C51N, Jun. 2017
Harris CDP65C51, Jan. 1991 //flow control explained.

;---

Note:
For consistence with Frank's notation, low_active signals are named foo#, not /foo.

Orientation for all the chip pictures: D3 pad is North.

Eagle 6.4 schematics for my schematic pictures in this thread,
just in case if somebody needs them.

Note: KiCad is supposed to be able to import these schematics,
unfortunately it doesn't seem to be possible to disable the layers 'name' and 'value' in KiCad schematics,
so making my schematics look nice and clean in KiCad will require some work, sorry.

A picture of the 8551R2 silicon, with the interesting areas marked.



Just as a reference, another picture of the MOS 8551R2 silicon without the markings.

8551R2 cheat sheet:

1a) XTAL clock generator //oscilator for the baud rate generator

When not using the external clock:
A 1.8432MHz crystal is connected to the XTAL1 and XTAL 2 pins.

BE WARNED that different chips have different oscillator circuitry inside.

To make the oscillator work in a reliable way, you may need to add some components at the XTAL pins.
What you are going to need depends on what sort of oscillator circuitry is inside the chip.

//Also note, that said oscillator circuitry tends to be different from what's in your usual PHI0\PHI1\PHI2 oscillators.

The MOS 6551 and Rockwell R6551 datasheets just skip that part.
For the MOS 8551 we can't tell: because we have no datasheet at all.

For WDC W65C51N, Rockwell R65C51 and Harris CDP65C51, there is some info in the datasheets:





;---

But now back to the MOS 8551.

Staring at this picture is supposed to give you a little headache:



Left: astable multivibrator.
Right: Butler oscillator (from the vacuum tube aera).

The red circles are added for highlighting why I had to put a picture of the 8551 oscillator concept
between the astable multivibrator and the Butler oscillator.

I never have seen an oscillator circuitry like that, I don't know anybody who has,
and there doesn't seem to be a similar thing in the internet (like on the homepage of radio amateurs).

But that's what's in the silicon. It's quite compact, and it's ingenious.

The "hot" part of the oscillator circuitry (which makes the crystal oscillate)
consists of two N FETs plus 4 PolySilicon resistors.
//Resistor values are estimated for a 3.5µm process by rule of thumb.

Basically we have a RS flipflop tied to the "collectors" of both FETs,
it generates a neat and symmetrical square wave in inverted and non_inverted form...
...which controls a driver that switches the XTAL signal either to GND or to VCC.

The XTAL signal then goes into "13) Baud rate generator".

//My guess is that the symmetrical build makes the oscillator more temperature stable.




;---

From the microscopic pictures, the Rockwell R6551 has pullups at the XTAL pads,
plus FETs switching the XTAL pads to GND, so it certainly has a different oscillator circuitry than the 8551.

We don't know if the MOS 8551 uses the same oscillator circuitry as the MOS 6551.

Would be nice, if somebody could measure the DC voltage levels at the XTAL pins when the oscillator is not oscillating
on the MOS 6551, the MOS 8551 and the Rockwell R6551.
Just to find out whether the MOS 6551 uses a similar oscillator circuitry as the MOS 8551 or not.

Now for a short cameo appearance of forum member Andrew Holme.

He kindly tried to do a LTSpice simulation of the "hot part" of the 8551 oscillator:



;--

From what I have seen, building crystal oscillators isn't a trivial topic:

If you are trying to build an amplifier, at some point it unintentionally might turn into a reliable oscillator.

But when you are _intentionally_ out to build a reliable oscillator, it seems to have sort of a habit not to work at first try.

1b) bias generator

In all of the HMOS-II chips we had a generator for the negative bias voltage, and the 8551 is no exception.

Basically we have a ring oscillator which is built from 5 inverters,
R1..R4 and C1..C4 set the frequency.

There is a driver attached to said ring oscillator.
The output of the driver goes through a big capacitor with two rectifier diodes attached,
and that's all there is to it.

Comment:
From my experience, best practice for a chip dissection is
to do clock generation and bias generator first,
then the bus interface and the address decoder,
(from there it's easy to figure out which register Bit goes where).
Then the buffers/drivers related to the rest of the pads,
and from there "the rest" of the circuitry between the registers and the pads.

Unfortunately, for the 8551 "the rest" had turned out to be a lot of stuff.

;---

2a) RES#

RES#=LOW puts the chip into hardware reset.

At the RES# pad, we have the usual ESD protection.

The low_active signal from the RES# pad goes through an inverter,
then through a non_inverting super buffer,
and becomes the high_active RES signal.




;---

2b) CS#

CS0=HIGH AND CS1#=LOW selects the chip.

At the CS0 amd CS1# pads, we have the usual ESD protection.

The low_active signal from the CS1# pad goes through an inverter,
and then together with the high_active CS0 signal into a NAND gate,
which emits the low_active CS# signal that goes into "6) address decoder".




;---

2c) R/W#

R/W#=HIGH: CPU reads from data bus
R/W#=LOW: CPU writes to data bus

At the R/W# pad, we only have the usual ESD protection,
the R/W# signal directly goes into "6) address decoder".




;---

2d) PHI2

At the PHI2 clock input pad, we have the usual ESD protection.

The high_active signal from the PHI2 pad goes into the chip.
Also, it goes into an inverter which generates the low_active PHI2# signal.

//Note, that PHI2# is different from PHI1.




;---

2e) IRQ#

Low_active "open collector" interrupt output signal of the 8551.

We just have a FET, switching the IRQ# pad to GND.
The high_active IRQ signal which goes into the gate of said FET
is generated in "7a) Status register, Bit 7".

3a) A0

A0 and A1 are the address line inputs for selecting
which 8551 register is going to be read or written.

Circuitry related to the A0 and A1 pads is pretty similar,
so we just focus on A0.

At the A0 pad, we have the usual ESD protection.

The high_active signal from the A0 pad goes through an inverter,
and from there into an inverting super buffer
(which generates the high_active A0in signal)
and into a non_inverting super buffer
(which generates the low_active A0in# signal).

A0in and A0in# go into "6) address decoder".




;---

3b) D0

The D0 pad connects to the external data bus.
Same thing for D1..D7.

Circuitry for D0..D7 is pretty similar, so we just focus on D0.

At the D0 pad, we have the usual ESD protection.

On the "write side", the high_active signal from the D0 pad
goes through an inverter, which feeds the low_active D0#
internal write data bus line.

;...

On the "read side", a push/pull driver is switching the D0 pad
either to GND or to VCC.

The driver FET which switches D0 to VCC is controlled by
a NOR gate with push/pull output.
Low_active control signal OED# enables the FET,
and goes into the NOR gate together with the low_active D0out#
read data bus line.

The driver FET which switches D0 to GND is controlled by
another NOR gate with push/pull output.
Low_active control signal OED# enables the FET,
and goes into the NOR gate together with the inverted
low_active D0out# read data bus line.

OED# (output enable data) is generated in "6) address decoder".

Note, that the read data bus lines have simple pullup FETs to VCC.
The pullups are integral part of "10) Control register".

//The 8551 uses no precharge mechanism for the read data bus lines.

4a) RxC //input or push_pull output, no pullup



If CTL4 (Control register Bit 4) is 0,
the RxC pad is the external input for the 16* RX clock.

Means that you send a clock which is 16* the Baud rate into the RxC pad,
and this becomes the clock for the RX (receiver) part of the 8551.

At the RxC pad, we have the usual ESD protection.

The signal from the RxC pad goes through an inverter,
and from there as RxCin# into "13) Baud rate generator.

In "13) Baud rate generator", there is a 2:1 multiplexer
controlled by CTL4, which then routes the clock signal to the RX part.

;...

If CTL4 (Control register Bit 4) is 1,
the 8551 gives out 16* RX clock generated by the Baud rate generator.

In this case, 16* RX clock is the same as 16* TX clock,
and the clock signals are generated by the Baud rate renerator.

To be more specific: the 8551 just gives out the TX clock TX_CLK16#.

Problem is, that the Baud rate clock and PHI2 are different clock domains.
When just enabling the output driver for the RxC pad with CTL4,
there is a chance that there might be a glitch in the output signal.

To prevent such a glitch, there is a RS flipflop which is set
when the control register is written, and cleared when TX_CLK16# is LOW.
//Most of the RS flipflops in the 8551 are built with NOR gates,
//but this particular RS flipflop is built from NAND gates.

The output of said RS flipflop goes together with TX_CLK16# into a NOR gate
(for gating the clock output), then into an output driver which isn't
much different from what we had in "3b) D0".

CTL_4#, the low_active output enable signal for the RxC pad driver,
is just the inverted output from the CTL4 register Bit.
The inverter which generates CTL_4# is located in
"12) Control/Command register output decoding".

4b) RTS# //"open collector" output with pullup

Wikipedia: RTS: DTE (computer) requests the DCE (modem) prepare to transmit data.

MOS6551 datasheet:
"The RTS# (low_active) output pin is used to control the modem from the processor.
The state of the RTS# pin is determined by the contents of the Command register."

;...

Signal CMD4#3#2# is generated in "12) Control/Command register output decoding".

It goes through an inverting super buffer, then controls a FET which switches the RTS# pad to GND.
Also, there is a pullup FET to VCC at the RTS# pad.

The RTS# pad only goes high if:
CMD4=0 AND CMD3=0 AND CMD2=0
AND the TX shift register is empty
AND TX transmits no BRK.

4c) TXD, CTS#

First about CTS#: //input, no pullup

Wikipedia: CTS: DCE (modem) is ready to accept data from the DTE (computer).

MOS 6551 datasheet: (Clear to Send)
"The low_active CTS# input pin is used to control the transmitter operation.
The enable state is with CTS# low.
The transmitter is automatically disabled if CTS# is high."


//Picture borrowed from Wikipedia.

In the 8551, CTS#=HIGH is _not_ a nice and polite way to stop a train of outgoing data.

CTS#=HIGH _instantly_ forces the TXD pad high, no matter whether a transmission is in progress or not.
Also, CTS=HIGH _instantly_ clobbers all of the Bits in the TX shift register to HIGH.

Means if a transmission is in progress while there only is a tiny HIGH spike at the CTS# pad,
that part of the data stream is corrupted/lost, and the Status register won't tell you about it.

For practical use of the chip, I think it might be a good idea to permanently tie the CTS# pin to GND...
...just to be on the safe side.

;---

Now for TXD: //"open collector" output with pullup

Wikipedia: TXD: Carries data from DTE (computer) to DCE (modem).

6551 Datasheet: (Transmit Data)
"The TXD (high_active) output line is used to transfer serial NRZ (non-return-to-zero) data to the modem.
The LSB (least significant Bit) of the Transmit Data Registeris the first Data Bit transmitted
and the rate of the data transmission is determined by the baud rate selected".

Again: CTS#=HIGH instantly forces TXD to HIGH.

;---

Now for the circuitry "between" the CTS# pad and the TXD pad:

At the CTS# pad, we have the usual ESD protection.
The low_active CTS# signal goes into "17) TX control", for causing some more mayhem there.

TXDout, the high_active serial data output signal which is generated in "17) TX control",
goes together with CTS# into a NOR gate with push/pull output.
Said NOR controls a FET which switches the TXD pad to GND.
Also, there is a pullup to VCC at the TXD pad.

4d) DTR# //"open collector" output with pullup

Wikipedia: DTR: DTE (computer) is ready to receive, initiate, or continue a call.

MOS 6551 datasheet: (Data Terminal Ready)
"This output pin is used to indicate the status of the 6551 to the modem.
A LOW on kow_active DTR# indicates that the 6551 is enabled and a HIGH indicates it is disabled.
The processor controls this pin via Bit 0 of the Command Register".

CMD0=0: transmitter and receiver disabled, DTR#=HIGH.
CMD0=1: transmitter and receiver enabled, DTR#=LOW.

The low_active CMD_0# signal goes through an inverting super buffer,
which controls the FET that switches the DTR# pad to GND.
Also, there is a pullup to VCC at the DTR# pad.

Signal CMD_0# is the inverted output of CMD0 (Command register Bit 0),
the inverter is located in "12) Control/Command register output decoding".

4e) RXD //input, no pullup

Wikipedia: RXD: Carries data from DCE (modem) to DTE (computer).

MOS 6551 datasheet: (Receive Data)
"The high_active RXD input line is used to transfer serial NRZ data into the ACIA from the modem, LSB first.
The receiver data rate is either the programmed baud rate or the rate of an externally programmed receiver clock.
This selection is made by programming the Control Register".

//For more details on external RX clock, see "4a) RxC".

At the RXD pad, we have the usual ESD protection.

The high_active signal from the RXD pad goes through an inverter,
and from there it goes as low_active RXDin# into "8c) RX data register input".

5a) DSR#, DCD# clock generation

Short form:
during a Status register read,
or when RX and TX are disabled with CMD0=0 (like after a hardware reset),
high_active control signal DSR_DCD_CK makes the DSR# and DCD# edge detection latches transparent.

//If there was a change in DSR# or DCD# after DSR_DCD_CK goes low, this generates an IRQ.

Please see "5b) DSR" and "5c) DCD#" below in the text.

;---

Long form:

A three_input NOR gate detects Status register read when OED#=0, A0in#=0, A1in=1.
Low_active signal OED# enables the data bus output drivers during a register read
with the chip selected, it is generated in "6) address decoder".

A0in# is the inverted A0 address input, A1in is the non_inverted A1 address input,
Status register has address $1.

The output of the three_input NOR gate which detects a Status register read
goes together with CMD_0# into a two_input NOR gate, which generates
the low_active DSR_DCD_CK# clock signal.

An inverter generates the high_active DSR_DCD_CK clock signal from DSR_DCD_CK.

We need that clock signal in high_active and low_active form,
because the DSR# and DCD# edge detection latches in "5b)" and "5c)" are half_static.

The low_active CMD_0# signal is the inverted output of CMD0 (Command register Bit 0),
the inverter is located in "12) Control/Command register output decoding".