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BigDumbDinosaur
 Post subject: Re: 6502GPD-D
PostPosted: Tue Mar 14, 2023 10:40 pm 
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banedon wrote:
[edit] I've noticed some weirdness with anything using JSR, which I didn't have with the DIP. part. It seems to execute the the code, but the RTS/RTI jumps to random addresses, so I think there is an issue with page 1 ($0100-$01FF). The AS7C4096-15JIN is supposed to be TTL compatible, so I don't thik it's the logic levels (which are TTL).

Have you posted a schematic somewhere?

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banedon
 Post subject: Re: 6502GPD-D
PostPosted: Wed Mar 15, 2023 12:33 am 
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It's definitely the adapter. If I run a program to write %10101010 to $0100 and set bit 0 of the status register (which lights LED 0) if it reads back ok, I can run at full speed (8 MHz) with the DIP in it and it'll work. If I do the same with the adapter, I can get it to work at 4 Hz (yes, 4 Hz) or lower. Can't see anything so far in the data sheet which might cause such an issue so far. It's late, so I'll reflow the pins tomorrow in case it's a bad solder joint.

Here's the adapter circuit diagram:

Attachment:
Untitled2.jpg
Untitled2.jpg [ 231.67 KiB | Viewed 492 times ]


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BigDumbDinosaur
 Post subject: Re: 6502GPD-D
PostPosted: Wed Mar 15, 2023 2:27 am 
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banedon wrote:
Here's the adapter circuit diagram...

I’m a little confused by what I am seeing: are there two SRAMs on that board? Also, that’s only the RAM. What about the rest of the circuit?

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Dr Jefyll
 Post subject: Re: 6502GPD-D
PostPosted: Wed Mar 15, 2023 3:23 am 
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BigDumbDinosaur wrote:
are there two SRAMs on that board?
BDD, I think the schematic is merely for the adapter board, shown upthread (here). So, one actual RAM connected to the footprint for another.

banedon wrote:
It's definitely the adapter.
OK, maybe. But using the adapter also entails using a different RAM chip... and it's that which might be causing the problem. For example, some of the newer RAMs are fast enough that they can respond to marginal conditions that a slower RAM would in effect gloss over and forgive.

-- Jeff

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BigDumbDinosaur
 Post subject: Re: 6502GPD-D
PostPosted: Wed Mar 15, 2023 4:45 am 
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Dr Jefyll wrote:
BigDumbDinosaur wrote:
are there two SRAMs on that board?
BDD, I think the schematic is merely for the adapter board, shown upthread (here). So, one actual RAM connected to the footprint for another.

Ah-so!

Quote:
banedon wrote:
It's definitely the adapter.
OK, maybe. But using the adapter also entails using a different RAM chip... and it's that which might be causing the problem. For example, some of the newer RAMs are fast enough that they can respond to marginal conditions that a slower RAM would in effect gloss over and forgive.

That’s where I think seeing the rest of the circuit might shed some light on a possible cause.

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Dr Jefyll
 Post subject: Re: 6502GPD-D
PostPosted: Wed Mar 15, 2023 5:45 am 
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banedon wrote:
It's definitely the adapter.
It's true that the adapter does lengthen the total length of the traces from the RAM to the mobo, so in that respect the adapter just might be responsible for some trouble. It'll be best to keep the traces short.

In pursuit of that goal, it would probably have been advantageous to judiciously scramble the address and data lines. For example, A0 of the SOJ RAM must surely attach to one of the address lines of the DIP RAM, but it needn't be A0. Instead it'll be better to choose whichever address pin is closest. You're free to criss-cross the address lines willy nilly, according to whatever scheme seems to yield the shortest traces. And the same is true when it comes to scrambling the data lines. This increased freedom may also lead to a less congested layout... something to keep in mind if you ever do a re-spin of the adapter PCB.

-- Jeff

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banedon
 Post subject: Re: 6502GPD-D
PostPosted: Wed Mar 15, 2023 7:23 am 
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Dr Jefyll wrote:
banedon wrote:
It's definitely the adapter.
It's true that the adapter does lengthen the total length of the traces from the RAM to the mobo, so in that respect the adapter just might be responsible for some trouble. It'll be best to keep the traces short.

In pursuit of that goal, it would probably have been advantageous to judiciously scramble the address and data lines. For example, A0 of the SOJ RAM must surely attach to one of the address lines of the DIP RAM, but it needn't be A0. Instead it'll be better to choose whichever address pin is closest. You're free to criss-cross the address lines willy nilly, according to whatever scheme seems to yield the shortest traces. And the same is true when it comes to scrambling the data lines. This increased freedom may also lead to a less congested layout... something to keep in mind if you ever do a re-spin of the adapter PCB.

-- Jeff

Here's the layout, with the silk screen and other details removed for clarity. My experience is that of a hobbyist, so I could be worng, but I'm not sure a reduction from 8MH to 4Hz is down to slightly longer traces - just seems likele such a radical operational drop.
I was thinking that it's more likely to be a poor solder joint, inappropriate part or faulty part?
Note: The IC's pin 1 is bottom right, where-as the adapter's pin 1 is top left. The bttom layer is flood filled and sued as ground.
Attachment:
D.JPG
D.JPG [ 78.93 KiB | Viewed 454 times ]


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banedon
 Post subject: Re: 6502GPD-D
PostPosted: Wed Mar 15, 2023 7:30 am 
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BigDumbDinosaur wrote:
Dr Jefyll wrote:
BigDumbDinosaur wrote:
are there two SRAMs on that board?
BDD, I think the schematic is merely for the adapter board, shown upthread (here). So, one actual RAM connected to the footprint for another.

Ah-so!

Quote:
banedon wrote:
It's definitely the adapter.
OK, maybe. But using the adapter also entails using a different RAM chip... and it's that which might be causing the problem. For example, some of the newer RAMs are fast enough that they can respond to marginal conditions that a slower RAM would in effect gloss over and forgive.

That’s where I think seeing the rest of the circuit might shed some light on a possible cause.

It's difficult, as they are on different sheets, but not too many. I'll rustle something together and post it.
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banedon
 Post subject: Re: 6502GPD-D
PostPosted: Wed Mar 15, 2023 7:57 am 
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I've converted the MPU/RAM/GLUE logic sheets into black & white and zipped them up - see below.
Don't think it's the design though, as the DIP part seems to work at 8MH, but the adapter runs only at 4Hz
Attachment:
Sheets.zip [278.18 KiB]
Downloaded 23 times


[edit] Please note that the WD, RD signals are marked as inbound on the CPLD, when they're actually outbound. On Sheet2_gluelogic-ConvertImage (Custom).jpg.


Last edited by banedon on Wed Mar 15, 2023 8:01 am, edited 1 time in total.

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BigDumbDinosaur
 Post subject: Re: 6502GPD-D
PostPosted: Wed Mar 15, 2023 7:59 am 
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banedon wrote:
Here's the layout, with the silk screen and other details removed for clarity...The bttom layer is flood filled and sued as ground.
Attachment:
D.JPG

That “flood fill” is not helping you in any way. All it’s doing is adding parasitic capacitance to the board.

Ideally, this part should be built on a four-layer board with internal ground and power planes. Such an arrangement will produce the quietest layout, with the advantage of not having to route power and ground. If two layers are necessary, then power and ground should be routed by the shortest and most direct paths possible.

In either case, a 0.1 µF MLCC should be placed so its connection to the power pin of the SRAM is as short as physically possible. Also, make the ground path for the capacitor as short as physically possible, but give priority to the “hot” lead. A bypass capacitor on the main board is not sufficient, as it will be too far away from the SRAM’s VCC pin.

The RAM you are using should easily handle a 25-30 MHz system. Your actual operating limit will be dictated mostly by construction, as well as propagation delay in the glue logic. Given that this adapter takes the MPU’s buses off the main board, I’d consider Jeff’s suggestion that you mix up the address and data lines to produce the shortest possible traces.

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BigDumbDinosaur
 Post subject: Re: 6502GPD-D
PostPosted: Wed Mar 15, 2023 8:11 am 
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banedon wrote:
I've converted the MPU/RAM/GLUE logic sheets into black & white and zipped them up - see below.
Don't think it's the design though, as the DIP part seems to work at 8MH, but the adapter runs only at 4Hz
Attachment:
Sheets.zip

[edit] Please note that the WD, RD signals are marked as inbound on the CPLD, when they're actually outbound. On Sheet2_gluelogic-ConvertImage (Custom).jpg.

Have you observed /CE, /OE and /WE at the SRAM’s pins to see the voltage levels when the device is selected and accessed? Are you sure your chip select logic in the CPLD is correct? Also, are you sure your wait-stating is not doing something hinky?

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banedon
 Post subject: Re: 6502GPD-D
PostPosted: Wed Mar 15, 2023 8:13 am 
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BigDumbDinosaur wrote:
banedon wrote:
Here's the layout, with the silk screen and other details removed for clarity...The bttom layer is flood filled and sued as ground.
Attachment:
D.JPG

That “flood fill” is not helping you in any way. All it’s doing is adding parasitic capacitance to the board.

Ideally, this part should be built on a four-layer board with internal ground and power planes. Such an arrangement will produce the quietest layout, with the advantage of not having to route power and ground. If two layers are necessary, then power and ground should be routed by the shortest and most direct paths possible.

In either case, a 0.1 µF MLCC should be placed so its connection to the power pin of the SRAM is as short as physically possible. Also, make the ground path for the capacitor as short as physically possible, but give priority to the “hot” lead. A bypass capacitor on the main board is not sufficient, as it will be too far away from the SRAM’s VCC pin.

The RAM you are using should easily handle a 25-30 MHz system. Your actual operating limit will be dictated mostly by construction, as well as propagation delay in the glue logic. Given that this adapter takes the MPU’s buses off the main board, I’d consider Jeff’s suggestion that you mix up the address and data lines to produce the shortest possible traces.

The PCB has two such capacitors (one for each set of VCC/GND pins) with the positive end adjacent to the power pin for that side.
Good to know about the flood fill groun plane. I went for the 2 layer board option due to sheer cost considerations because I was getting a lot of PCBs manufactured (there were 5 or 6 different designs) and I live in the UK, so prices are a bit wild. Hopefully that design vs cost decision hasn't come back to bite me on the bum. BTW the ROM reads correctly at 8MHz with this adapter fitted - it's just the adapter which seems to have the problem.
If it really does seem to be down to the the layout then I'll have to redesign it with Jeff's and your suggestions in mind. I just cannot get over the collosal drop in performance betweena dapter and DIP IC.
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banedon
 Post subject: Re: 6502GPD-D
PostPosted: Wed Mar 15, 2023 8:21 am 
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BigDumbDinosaur wrote:
banedon wrote:
I've converted the MPU/RAM/GLUE logic sheets into black & white and zipped them up - see below.
Don't think it's the design though, as the DIP part seems to work at 8MH, but the adapter runs only at 4Hz
Attachment:
Sheets.zip

[edit] Please note that the WD, RD signals are marked as inbound on the CPLD, when they're actually outbound. On Sheet2_gluelogic-ConvertImage (Custom).jpg.

Have you observed /CE, /OE and /WE at the SRAM’s pins to see the voltage levels when the device is selected and accessed? Are you sure your chip select logic in the CPLD is correct? Also, are you sure your wait-stating is not doing something hinky?

I'll be 'scoping it tonight (got work shortly), although the wait state has always been observed as high (so off) and PHI2 runs at full speed. The 'RAM=non-wait state / ROM=wait state' hasn't been enabled in the CPLD yet, so it all runs at the same speed. I wanted to get the RAM adapter fully tested before implementing that so as not to mix testing and make fault finding harder.
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BigDumbDinosaur
 Post subject: Re: 6502GPD-D
PostPosted: Wed Mar 15, 2023 8:28 am 
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banedon wrote:
I just cannot get over the collosal drop in performance betweena dapter and DIP IC.

Well, if it’s any encouragement, I have POC V1.3 running at 16 MHz with the SCSI host adapter plugged into the expansion socket. The host adapter is several times the size of your SRAM adapter, and not only has the SCSI controller ASIC (a PLCC84 part) and a buffer/driver connected into the MPU buses, the real-time clock is on it and is also connected to the buses. The PCB is four layers and stability is pretty good. :D Current system uptime is 89 days.

Given all that, if I were working on your project, I’d be carefully inspecting the SRAM adapter PCB layout, and also the layout around the point on the main board where the SRAM adapter is interfaced.

When you get a chance, please post the CPLD code so I can see how you are handling /CE, /OE and /WE.

BTW, another SRAM that will work in your application is ISSI’s IS61C5128AL-10KLI. Same size, but slightly faster at 10nS.

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GARTHWILSON
 Post subject: Re: 6502GPD-D
PostPosted: Wed Mar 15, 2023 8:49 am 
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Although the copper pours absolutely do not qualify as a ground plane for this kind of work, they definitely are not to blame for reducing the operating frequency to 4Hz which is two octaves below the lowest audible frequency (although the harmonics involved with making a 4Hz square wave are definitely audible).  This is especially true for such a small board.  I can't think of what could reduce it so extremely!  The page of the 6502 primer about avoiding AC performance problems is something that deserves attention, but it will be something to digest gradually.  It falls in the category of "not urgent, nevertheless important" (when you're dealing with ICs that have very fast slew rates at their outputs).  The last seven links in the bulleted list at the bottom of the page are to videos of lectures by people who understand this stuff far better than I, and they also explode some myths that have stubbornly persisted for decades and that continue to trip up relatively experienced engineers.

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