Hi guys

I've got a couple of projects which I've started up again, one for the 6502 and the other a 65816. This is the 6502 one (the 65816 comes next when this one is completed) and I thought I'd share the progress:

I/O:
The PCB is relatively simple, with no real I/O on it, but instead relies on 3 PCI physical slots, each of which can be seen as 2 logical slots. There is a bank of 8 LEDs which are mapped into the I/O space and controlled by a physical latch. There's also a 4 switch DIP input, again, mapped into the I/O space.

Clocks:
The clock (PHI2) has been tested up to 8MHz (cannot test faster as that's the fastest DIP SRAM that I presently have), and can be clock stretched for slower devices, whilst maintaining a global clock (this is thanks for BDD's clock stretching design).

Memory map & paging:
(this is presently being modified as required, so isn't fixed as yet)
0000-0FFF : RAM, Zero page & stack + work area, always mapped in
1000-1FFF : RAM, always mapped in by default, can be marked as pagable using MR
2000-2FFF : RAM, always mapped in by default, can be marked as pagable using MR
3000-3FFF : RAM, always mapped in by default, can be marked as pagable using MR
4000-BFFF : RAM, pagable
C000-C0FF : I/O & register space, always mapped in
C00x : MR, register, read/writable
C01x : PDR, register, read-only
C02x : FWR, register, lower 4 bits, read-only
C03x : SR, register, write-only
C04x : INTSR, register, read-only
C0Fx : BR, register, bank (paging) register, lower 4 bits, read/writable
C100-CFFF : RAM, OS ROM working area, presently pagable
D000-FFFF : OS ROM, may be shadowed into bank 0 RAM using MR

Banks:
0 - 7 : RAM
8 - 13 : PCI slots (6 logical slots)
14 - 15 : Optional OS ROM pages as the OS ROM will be (minimum) 256KB - possible rom paging register may be implemented to change which part of the OS ROM is mapped in by these slots, or bits 0 & 1 of MR may be utilised. This may not be done depending on the need for it.

Registers (presently mapped at C000 to C0F0):
MR (Memory Register): Manage writing to underlying RAM beneath the ROM area, ROM full shadowing, paging control of 1000-3FFF areas. Read/wriable.
PDR (PCI Detection Register): Bits 0 to 5 reflect the detected PCI cards (one bit per logical 'slot', so 2 bits per physical slot). Read-only.
SR (Status Register): Mapped to the 8 LEDs on the PCB. Read-only.
INTSR (Interrupt Status Register): The IRQ and NMI signals from the physical PCI slots are mapped here. Read-only.
BR (Bank Register): Contains (and controls) the current (page) bank number. Read/writable.

IRQs & NMIs:
Each physical PCI slot has one IRQ line and one NMI line.
The card will AND all of the IRQ signals for the ICs on it and feed the result down this line (same with NMIs). The 6502'S ISR is then expected to consult INTSR to see which type of interrupt (IRQ or NMI) and which slot generated it.The 6502's IRQB and NMIB lines will still be set/cleared as standard.
The PDR consists of:
Bits 0-2 are IRQs for PCI slots A,B,C. Bits 3-5 are NMIs for PCI slots A,B,C. A one in a given bit field indicates the source of an IRQ/NMI.
The ISR should check both the INTSR and PDR.
The INTSR always reflects the interrupt signals as they presently are, so clearing the source of an interrupt clears the appropriate bit in this register.

Buses:
Address lines A0 to A19, with A16 to A19 seen as the 4 bit banking address.
The databus is, as ever, 8 bits, with an optional pull up or pull down bus resistor network on the PCB (not presently needed/fitted).

PCI slots
The PCI slots have 50 signals, which cover the full (A0-19) address & (D0-7) data buses, the GCLK and PHI2 clocks, the RWB, RD and WD signals, IRQ and NMI signals, BE and RDY signals (capable of shutting down the 6502 in favour of an offbaord MPU), two 'logical' slot detection lines, WSE (wait state enable) line, Reset (RESB), 2x VCC and 4x GND power/ground connections.
Each logical card is expected to provide (at a minimum) ROM space for a descriptor table, address glue logic, control of WSE and detection signals.
Banks 8 to 13 (1 bank per logical slot) are allocated to the PCI slots.

Signal Breakout/Indicators:
A0-15 - 20 pin IDC socket
A16-A19 - Discrete pins
D0-7 - 10 pin IDC socket
RESB, IRQB, NMIB, RWB, ROM, RAM - Discrete pins
Aux power out - 3 sets of VCC & GND connections.
JTAG for CPLD - 2x4 pin header
PHI2, GCLK, WSE - Discrete pins
2x 'scope grounds - Discrete pins

Jumpers:
Isolation jumpers for GCLK and PHI2
WSE mode jumper to set +1 or +2 extra cycles when WSE asserted
A17 and A18 isolation jumpers for the OS ROM so a 1,2 or 4 Mbit ROM may be fitted (all must be 32 pin DIPs though).
Jumper pad for the optional data bus termination bus resistor to set it to pull up or pull down as needed.

Testing:
LEDs: Can be written to at 8MHz
ROM shadowing: CPLD logic present, but untested
IRQS/NMIs: CPLD logic present, but untested
Banking: RAM banks 0 to 7 tested ok at 8MHz for 4000-BFFF
PCI slots: Untested as yet. I have had a PCI card with serial and VIA on it to test it with, but the card isn't populated as yet.
Power usage is at just over half a watt (116mA @ 5V = 580mW)
Wait stating: CPLD logic present, but untested until I have RAM which is faster than the OS ROM.

Additional possibilities:
I would like to implement a system 16 or 32 bit register attached to a (non-ripple) counter, which sets off an IRQ when it reaches zero. I'm not sure if the CPLD has enough terms left for this as I didn't think of it until after the PCB was manufactured. We'll see. The good news is that the GCLK and PHI2 clocks are linked to two of the three CPLD's clock pins, thus saving terms.

Some pictures:

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

very fancy project! though i gotta say when you said "PCI slots" i thought you meant ACTUAL PCI slots, you know the ones on old PCs with a 1.27mm pitch and 116 contacts.
it would've been really impressive to be able to use 32-bit PCI cards in a 65c02 SBC.

i like the idea of each expansion card having some kind of identification on them so the system is able to automatically determin what is installed. but a whole ROM just to identify a card seems a little overkill IMO. wouldn't it be enough to for example have 1 or 2 74x244's with hardwired (jumper/DIP switch) inputs? the CPU could then read those out to get an 8 or 16-bit ID number which would be unique for each card type.

on a side note, my own 65816 SBC's CPLD had just enough logic in it for a 26-bit counter that increments using the VIA's T1 timer (the mode with PB7 flipping each time the Timer reaches 0), that slow clock signal goes into the CPLD and gets divided by 8 and then used to generate an IRQ for the CPU and increment the internal counter.
to avoid read errors (since it could increment while reading) once the CPU starts reading the low byte, the whole value of the counter is saved in a temporary register, which allows the CPU to then read the other 2 bytes without worrying about the value changing.

so, if you include a counter in your CPLD i'd recommend also having a temporary register inbetween which of course pretty much doubles the macrocell usage.

My thinking on the counter was simply it would be set, started, count down, generate IRQ when finished - no plan to allow it to be read. However, if I want it read then I'd have to do what a VIA does, which is what you're describing with the copy register.

With regards the PCI slots. Yeah, I should call them something different. I started off calling them that for lack of a better description, and it stuck. I will probably rename them as I didn't put 'PCI' on the silk screen.
The reason for the need for a ROM on each card is it hold the ISR and any routines that the card needs to run. This is because the slots are the real centre of what the SBC is all about and I wanted to make them as usable as possible. I suppose you could have a card without a ROM and instead have the logic that you describe mapped into the memory map - maybe have both systems, determined by a byte type read from a specific location.

Following with interest.

My thoughts are similar to most complex designs and that's not the actual hardware but the software to drive the system as a whole. Have you a concept of an operating system and what sort of applications you might want to run on it?

I saved myself a few braincells in a way by having the aim of running initially Applesoft BASIC then BBC Basic, so making my systems adaptable to those was an aim and one that I felt was easy to achieve.

Taking full advantage of all that banked/pagable RAM is the challenge here, I think.

Cheers,

-Gordon

_________________
--
Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

My main motivation for building this project is for testing ideas via the expansion slots without having to design an entirely new SBC each time. All I need to do once this is up and run running is design the add-on cards . However, I could make a version with a different memory topology which works with BBC Basic - although it'd probably need just a little bit of tweaking!

oh i see, so it work like a write-only version of the VIA's T1 timer.
i personally like a continuously counting readable counter more as it allows you to effectively run multiple timers at once, which (i think) isn't possible with a single shot counter.
for example a program that calls some function every 5 seconds and another every 12 second, you could do something like this:

technically you could use the VIA's T1 timer in continuous mode to do something similar, but T1 is only 16-bits wide which makes it way too small to be useful for any timespan in milliseconds or larger (atleast on faster systems).
man how i wish there was an upgraded VIA with 32-bit timers and better feature parity between T1 and T2. a man can dream....


i'm interested to see what kind of expasions you'll experiment with. from video, sound, storage, to more different ideas like a co-processor card, or an interface to some older Floating Point Unit.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

That's the method I'm working on atm. I've presently got a 16 bit count down timer coded up for the CPLD. Am going to add a roll over enable, where it reloads the original value. Also, it will generate an IRQ with the ability to clear that.

In the meantime, I'm working on an SOJ36 to DIP adapter which will allow me to put faster SRAM in the SRAM DIP socket. Downside is that I didn't extend the SOJ pads, so I'm struggling to solder the ICs on. I've got a Miniware MHP30 Hot Plate Preheater on the way which I'm hoping to use to reflow using a solder paste syringe.

Here's a couple of pics. If anyone is interested, I wil be willing to post the gerbers once I've tested that these adapter boards work:

Got the the PCB soldered up. Was a bit of a pain getting it done without solder bridges, but ti fits, works so far. The IC used is a 15ns AS7C4096-15JIN. I'll now get to test the WSE by kicking up the clock and then see if it stretch ok for the ROM.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Yep, ended up using solderbraid in the end . Things were just a bit on the small side and, like you, my eyeballs don't cope well any more.

[edit] I've noticed some weirdness with anything using JSR, which I didn't have with the DIP. part. It seems to execute the the code, but the RTS/RTI jumps to random addresses, so I think there is an issue with page 1 ($0100-$01FF). The AS7C4096-15JIN is supposed to be TTL compatible, so I don't thik it's the logic levels (which are TTL).