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PostPosted: Tue Apr 08, 2003 12:41 am 
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Location: ChristChurch New Zealand
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I have just found out that I can edit and delete any silly questions, incorrect information etc...

This page I'll keep here a little longer but no more replies to this forum thread thanks!

from N Pastoll :oops:
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Ok say I have a 6502 running at 1 MHz

I just want to clarify the meaning of ticks and cycles:--

* This means that its running at 1,000,000 cycles per second right?!

half of that being in duty cycles if using 50% duty cycle.


I'm new to design of logic circuits and now I understand that there is a smaller value called the tick?!

What exactally is a tick - and how many of them do you have per cycle or of the total freq? which ever is the right way to calculate..


thanks

:roll:

P.s. From what I have found I think a tick is time taken for a logic gate to calculate and change state of output if necessary.

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Last edited by 1202 on Wed Apr 09, 2003 8:17 am, edited 2 times in total.

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PostPosted: Tue Apr 08, 2003 2:06 am 
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When designing e.g. an address decoder - is it very important to find the total propagational delay of the components so that the total delay doesnt exceed duty cycle? somthing like that...

?? Hmm A little confusion in mind

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PostPosted: Tue Apr 08, 2003 2:19 am 
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http://www.webopedia.com/TERM/c/clock_tick.html

anyone want to add to this! definition.

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PostPosted: Tue Apr 08, 2003 10:26 am 
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A 6502 running at 1MHz wants a clock at 1MHz with a 50% duty cycle. 1MHz means there are 1 million complete waveforms (or cycle - the clock signal goes low for a bit, then high for a bit) in each second. The 50% duty cycle means that in one cycle the signal spends 50% of the time high. That works out to 500ns low, then 500ns high.

In this context, 'tick' would be synonymous with 'cycle'. There will be 1 million ticks per second. But no one says 'tick'.

Logic gates (and everything built from them) have a propagation delay. That's the time you have to wait from changing the inputs until the output is guaranteed to be correct. It's not related to the clock at all.

Let's say you have a simple computer. I'll make it based on the non-existant 6599, because I can't remember the exact details of the 6502 bus timing. With the 6599 I can just make it up :-)

If you look up the 6599 datasheet, you'll find that it puts an address on the address bus at most 100ns after the clock has gone from high to low. It needs the memory to place valid data to be on the bus at least 150ns before the next high-to-low transition.

Attached to the 6599's address outputs is an address decoder. That recognises certain ranges of addresses, and sends 'select' signals to the appropriate memory chips. It has a propagation delay of 200ns.

Then there's the memory. After it has a good address, and a 'select' signal, it takes 600ns to read the data and put it on the data bus.

So will it work? Call the first high-to-low transition of the clock time 0. At 100ns, the 6599 gives us the address. At 300ns (200ns later), the address decoder gives us a select signal. At 900ns, we get the data back from the memory. But that's less than 150ns before the next high-to-low transition (which will occur at 1000ns). So no, it won't work.

If we used a faster memory (which gives us data after 400ns), the data will be on the bus 200ns earlier. That's well within the limit, so that memory will work.

Don't take these numbers literally, by the way. They're all invented purely for the example. And there's endless details I've left out.


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PostPosted: Wed Apr 09, 2003 6:21 am 
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1202 wrote:
* This means that its running at 1,000,000 cycles per second right?!


Right.

Quote:
half of that being in duty cycles if using 50% duty cycle.


Wrong. At least, your interpretation is wrong.

Duty cycle (note the singular) specifies the ratio of time high to the total time of a single cycle. So if you have a clock signal that is 3us long while high, and only 1us long while low, it has a duty cycle of 75%. If it is high only 1us, and low for 3us, the duty cycle is 25%. If it's symmetrical, then the duty cycle is 50%.

Note that the 6502 and 65816 processors prefer a 50% duty-cycle clock. That is, the time spent high is the same as the time spent low.

Quote:
I'm new to design of logic circuits and now I understand that there is a smaller value called the tick?!


No. The "tick" is an arbitrary unit of time measurement. For example, in the Commodore-Amiga series of computers, "ticks" occured 60 times per second in the NTSC hardware, and 50 times per second in the PAL hardware. Ticks were used to keep track of the time of day. They had nothing at all to do with the CPU or other motherboard hardware.

Sometimes, ticks are called jiffies, especially by those who grew up using the old 8-bit Commodore computers (e.g., the Commodore 64, +4, and 128).

Quote:
P.s. From what I have found I think a tick is time taken for a logic gate to calculate and change state of output if necessary.


No, this time is called propegation delay.


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