265EB for the C64

265 Expansion Board for the Commodore 64.

The project consists in building a cartridge that would be plugged in the expansion board of a C64, and would be able to access its internal memory and chips by the means of DMA'ing the bus. The cartridge will have has a w65c265s MPU.

The memory of the C64 will be mapped in the bank $40 (decimal 64) of the '816 core inside the '265: $40:0000-$40:FFFF

The MPU will get its power and its clocks from the C64 expansion port. At a first stage, I will try to get the MPU working by itself using those signals. The MPU will communicate externally with the user by using its internal serial port as seen in the single board computers WDC sells based on it.

The MPU needs a slow and a fast clock signals (CLK and FCLK). If the datasheet is right, CLK can be up to 1/4 the rate of FCLK. That's why DOTCLK (~8mhz) is being halved by using a counter down to ~4Mhz, becoming FCLK. And for CLK, the internal PHI2 clock output will be used, because it ticks at ~1Mhz. If not possible, an independent ~32Khz quartz will be put on the cartridge.

The circuit of the clock divider is this one:

The memory of the C64 is shared between its video chip (VIC-II) and its CPU (6510). The VIC-II access the memory during the low phase of PHI2, and the 6510 during the high phase of PHI2. Regularly the VIC-II needs extra access to the memory, so it halts the 6510 the time it needs to.

This has to be addressed somehow. The MPU (The 265 in the cartridge, I mean) must be capable of both:

• Be paused by the VIC-II, and
• pause the internal 6510

when accessing the internal C64 memory.

As this should be happening only in that conditions, but not when the MPU is accessing its internal memory, or any other external memory out of the range of the $40 bank, I tought of this circuit, that would only get the MPU's RDY input low when that conditions are met:

• The $40 bank is being accessed, and
• the BA line is being held low by the VIC-II

, because it needs to access the same memory as the MPU wants to. Cannot tell if there is an easier way to to this.

And this pretty much what I've been able to think until now. Once I get the first stage done (this last circuit is not yet needed for that), I will think about syncing the MPU with the C64 internals.

I can't be certain either, and I don't have time to attempt to prove it, but I think our old friend De Morgan can help you get rid of most (if not all) of those inverters.

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Got a kilobyte lying fallow in your 65xx's memory map? Sprinkle some VTL02C on it and see how it grows on you!

Mike B. (about me) (learning how to github)

Yep, inverters into a NAND make an OR.

This is the way I found to be sure of getting that line low only and only if bit6 of program bank address was 1 and the others 0.

Do FCLK and CLK need to be synchronous? There could be a phase delay if PHI2 and dot clock/2 are used.

I think there's no wide 'or' gate.

A magnitude comparator 74'688 could be used to select the page, but this may be too slow. The page could be set with a dip switch then.

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http://www.finitron.ca

Not at all. They can be both different clocks even, because the internal CPU never uses them both at the same time.



My goal is having the page $40 hardcoded as a direct reference of being accesing the Commodore 64 internal memory. But of course it could be also page $01 or whatever. In any case, I want the system to be able to handle this automatically.

There is also a register in the '265 that allows to access the memory under certain chip selects by using CLK instead of FCLK, so the internal C64 memory would be accessed clocked by PHI2 and the rest of the memory the '265 access, would be accessed using FCLK.

But by now this is all theory until I start building. I'm waiting for some boards to arrive.

Ok. It seems this could actually work.

I've successfully booted the MCU by using the internal power and clock from the Commodore 64.



This is nothing to write home about, or is it? I put a 74HC161 counter as recommended and wired the fastest output to the FCLK input and the slower output to the CLK input. But I think it would be better to wire the CLK input directly to the PHI2 output instead of the counter's one, because that would ensure it to be in sync with the computer internal one.

It still does not interface the Commodore 64 internal memory.



The BE/RDY line is wired permanently high. The next step is having the MCU be in sync with the video chip.

I managed to get the '265 working at DOT clock of the C64, PAL version. (~7.88Mhz). This, working in stand alone mode: not intervention of the BA signal pulling w65c265s' RDY signal low.

My logic analyzer is one of those chinese saleae clones, working at 24Mhz, so I had to work in C64's PHI2 clock: ~0.985Mhz in PAL mode.

The setup is: +5V and GND from the C64 goes to +5V and GND of the PCB.

PHI2 from the C64 goes to
- the clock input of a 74hc161
- the 1A,1B inputs of a 74ls00

1Y output from the 74ls00 goes to FCLK of the '265s

Qd output of the 74hc161 goes to CLK of the '265s

BA from the C64 goes to the BE/RDY input of the '265s

With that setup, this is what I get:

The '265 sheet states: "If you want to stop the processor, you should pull BE low in the PHI2 high time for as many cycles as needed."

I think I did it:

And this way, I can boot the '265s and have it working in sync with the BA signal coming from the C64. This way, the CPU should be being stopped by this signal, but I can't check if that is being done properly.

Maybe by writing some code and have it running in the internal memory of the '265s it could be done.

Next stage should be to wire the 74hct245 chips to the system bus.

Is not the clock input to the '161 fed by the dot clock?

Otherwise FCLK and CLK would be slower than ph2.

I think BE needs to be tied to the address enable control (AEC) line of the VIC-II. The bus still needs to be available for up to three clock cycles after RDY is pulled low so that writes can occur. AEC off follows BA by three clocks.

_________________
http://www.finitron.ca

Originally it was, but I had to resort to PHI2 because my testing equipment is not fast enough to cope with capturing ~8Mhz clock pulses.

So PHI2 is directly connected to FCLK and at the same time as clock input to '161, that feeds CLK with its slowest output (Qd).


The BA output line in the expansion port is tied to that BA output in the VIC-II. BA requests the processor to stop.


Yes, this happens to ensure the processor ends its writes if it is that it's writing.

What I think I've achieved is to have the external CPU (eCPU) being stopped by the VIC-II as needed, regarding the clock part. But I still haven't connected eCPU to the internal memory of the C64, and that's where things are gonna get funny.

The /DMA line of the expansion port pulls low both BA and /AEC int the internal CPU (iCPU).

So I have to make eCPU to properly ask iCPU to stop an release its drivers in the same way VIC-II does but in the low phase of PHI2. And eCPU itself should be able to be stopped when the VIC-II needs to access the internal memory. That's what's next to come.

The problem is that the '265s external address and data lines does not tristate, so I have to use '245 for that.

Very interesting tread!

I tried to do something similar on the Vic-20, but didn’t have any BA signal (no need on the VIC-I). I ended up using the expansion as external memory.

It will be interesting to see how the C64 can be interfaced. Many people are looking for a «SuperCPU» like expansion since they are so hard to find (and expensive!). Keep up the good work!

@tokafondo : +1 for your approach!
any progress on this?