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PostPosted: Thu Oct 06, 2022 2:07 pm 
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My 6502 clock is 2MHz but I have some support IC’s only rated for 1MHz..
6522 VIAs and R6532’s specifically.

What’ll happen if I feed them 1MHz(same phase) while the 6502 is running at 2MHz?

What are the chances the old 1MHz non-C parts survive the overclocking to 2MHz? (I know the 6502A doesn’t mind 2MHz)

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PostPosted: Thu Oct 06, 2022 2:54 pm 
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AndersNielsen wrote:
What are the chances the old 1MHz non-C parts survive the overclocking to 2MHz?
There's no threat to their survival. IOW, they won't be damaged. And there's even a pretty good chance they'll work. :)

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PostPosted: Thu Oct 06, 2022 5:08 pm 
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This is exactly how the BBC Micro worked - there was a 1MHz clock (called "1MHzE" in the schematics) that fed the VIAs and maybe some other clocked chips, while the CPU ran at 2MHz (one level further up the divider chain of a 16MHz clock). When talking to the VIAs, or other slow devices, the CPU clock was stretched to align with one cycle of 1MHzE. There were two possible stretching waveforms, depending on the relative phases at the start of the operation.

I've attached part of the schematic - the full thing is here: https://mdfs.net/Info/Comp/BBC/Circuits/BBC/bbc.gif

The signal from bottom left is a 2MHz clock; the one next to it (that clocks the bottom two flipflops) is 8MHz, which shifts some things out of phase a bit.

The signal coming down from the top just left of the middle comes from the address decoding, and goes high during phase 1 if a slow device is being accessed, and this then triggers the stretched cycle - I think it holds phi2 low until a rising edge on 1MHzE, then holds it high until the falling edge, and allows it to return to normal 2MHz operation afterwards.

It's always seemed a rather complicated arrangement to me, it may be possible to do it more concisely.


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PostPosted: Thu Oct 06, 2022 6:03 pm 
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gfoot wrote:
This is exactly how the BBC Micro worked [..]

It's always seemed a rather complicated arrangement to me, it may be possible to do it more concisely.


That’s hilarious! According to Wikipedia they managed to get state of the art RAM to allow double access at 2Mhz … but then they still had to jump through hoops like this for the IO.
I would’ve thought the 2Mhz rated IO would’ve been available by 1981.. maybe the extra logic was just cheaper?
Could also be a power issue - those 6522’s run rather warm at 2Mhz and maybe significantly less at 1MHz :)

I wonder how much power my sbc would need if it didn’t use CMOS ROM, RAM and most logic. 50 Watts for the beeb is a lot!

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PostPosted: Thu Oct 06, 2022 8:13 pm 
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Like Jeff suggested I'd just go ahead and try them at 2MHz. It won't hurt them.

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PostPosted: Mon Nov 21, 2022 11:56 am 
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gfoot on Thu 6 Oct 2022 wrote:
It's always seemed a rather complicated arrangement to me, it may be possible to do it more concisely.


Nowadays, it is trivial to find circuit diagrams for a dozen similar designs. In the the late 1970s and early 1980s, it was incredibly difficult to obtain information quickly or at all. Regardless, there is something distinctly "don't touch it, it's doing something" about Acorn's video circuitry. Despite tear-downs of rival designs, they persisted with a video circuit which has more components than a Sinclair ZX Spectrum. There is also a computer history video where Chris Curry explains that only one brand of tri-state buffer worked for the DRAM address lines. (I have no idea why they didn't use 74LS157, like the Spectrum.) Chris Curry also explained that TTL loads were exceeded by using a data bus pull-down resistor pack to simulate holding a finger to the board. (They only made 1.5 million of these things.) Other parts of Commodore and Acorn designs are crufty because they simultaneously use spare logic gates while skewing 8MHz clock or similar into a 150ns DRAM Row Address Strobe.

I solved this problem as unsolicited work for the Commander X16 project. I thought this would be particularly useful because it would allow 6522 timers to work independently of processor speed. This would solve a minor problem with PS/2 keyboard not working above 2MHz. It would also be useful for the multiple sound outputs and MIDI. (The 8 Bit Guy who started the Commander X16 is very enthused about 8 bit music and 1980s synthesisers.) I was surprised that my work was rejected, although it works best if the slow I/O range is contiguous. I don't believe that yet another suggestion to change the memory map (or 65816 compatibility) was appreciated. Whatever. I gave them first refusal and I'm not offended that they refused.

I solved this problem in a manner which is NMOS or CMOS compatible and works at arbitrary ratios, including ratios which are not integer. This is not original. I believe similar circuitry can be found in Amstrad computers before it became common in x86 designs. It is also highly likely that I have re-invented a subset of CMD SuperCPU functionality. Anyhow, after going slowly mad over three days, I eventually defined the scope of the problem in a manner in which the answer is trivial, one day to ensure that it resets into a useful state and one further day to check my work.

The solution is to use three flip-flops to implement a three state, one-hot, edge triggered state machine where one state is the idle state and the other two states allow the buses to mesh for a sufficiently long period to reliably convey a read or write. The tricky part is that each state inhibits the previous state and therefore the states only advance in one direction. (I strongly doubt this design principle scales gracefully.) Acorn's NMOS design is crufty, uses one unnecessary chip, only works in a 2:1 ratio and was re-designed for CMOS. However, they didn't have my hindsight or five days to work on the problem.

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