I'm creating a extended ROM/RAM board for my computer. Essentially it will have a 128KB RAM chip which will be mapped as 16 banks or 8K each. But for the first four banks (0-3) I want the option of using ROMs instead.

Coming from my CPLD are five chip enable signals (the CPLD logic ensures only one is enabled low at a time). CE4 selects the RAM chip. The first four (0-3) are routed to both the relevant ROM chip and the CE4 line for the RAM. Which chip is actually connected to each line is determined by a jumper. This is the circuit I came up with for each of the 0-3 CE lines.



The idea is that when the jumper is set to connect the ROM, that line won't affect CE4 in any way because it's not connected. There's a pull-up on the ROM's CE line which the CPLD pin can pull low.

When the jumper is set to connect the RAM, the pullup keeps the ROM quiet. Meanwhile, although the CPLD pin can pull CE4 low (due to the diretion of the diode), it can't drive it high (there's also a pullup on CE4 elsewhere that I forgot to add). This is important because theres are, effectively, five pins from the CPLD potentially connected to CE4, so it's important that none can drive the line.

At least, that's my theory. But playing arounf with various diodes on the breadboard I find that values are not everything I'd like them to be.

For example, with one diode (an SD103C Schottky), when controlling the ROM, I get 5V when the CPLD output is high (good) and 0.5V when low (which I figure is good enough). But when I'm controlling the RAM, and the CPLD pin is high, I'm still getting 2V on CE4.

As an electronics beginner, I'm still at the confused stage when it comes to diodes, so I'd appreciate any advice on suitable devices, problems with my circuit or what characteristics to look for on the data sheet.

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It sounds like there is something missing in your explanation. When you see the 2V on the RAM /CE what is connected to that line (are there 4 CLPD lines through diodes connected?) and what state are each of these connections in?

Maybe a complete schematic with a truth table would help.

Also, it may be far better to do this with active logic than use diodes.

Do teh CLPD chip select line drive other components or only RAM or ROM? If they are only controlling RAM or ROM chip selects which already have pullups on them then they should be set to open drain and the diodes will not be needed.

I think we need mope information.

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Bill

Sorry if I wasn't clear. Imagine four copies of the circuit I showed, each one controlled by a different pin on the CPLD (CE0 - CE3) and each going to a different ROM chip, but where the RAM /CE lines are commoned together. There's a fifth pin (CE4) from the CPLD also connected to the RAM /CE.

The idea is that if, say, bank 1 is selected, it will control the signal from the CPLD pin CE1. This will pull the CE1 pin low. Now, according to how the jumpers are set, this is either pull the /CE pin of ROM 1 low or pull CE4 (for the RAM) low.

However, because there are five signal lines connected to the CE4 line, and only one of them is going to be low at a time, the others will be at 5V. Without a diode on each line I'd end up with a short circuit.

Here's a more detailed schematic.

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Thanks for the schematic. It makes things clearer.

You won't get a short circuit if you set the CPLD outputs to open drain. You already have pull-up resistors where they need to be. Setting the /CE outputs to open drain will allow you to tie as many as you like together without diodes. It s called 'OR' tying.

So, with the current circuit, when you see the 2V are any /CE lines (other than CE4) attached to the RAM? Are any of those (including CE4) low at that time?

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Bill

If I were to have all the ROMs selected (via jumpers) where would be no problem. The problem arises when the jumpers are set so that the CE lines 0-3 (or some of them) control the RAM chip. Let's say all of them are. That means all CE lines 0-4 are connected to the RAM /CE. At any one time, four of those will be high and one low - that's where the short circuit comes in. So I put in the diodes so that the pins on the CPLD don't actually drive the lines when high, they only sink when low. Making the lines high is the job of the pullups.

I did a breadboard test of just one of these circuits. With a CRH02 diode, all seems to work as planned. When the control line is high, the RAM /CE is high, and when the control line is low the RAM /CE is low (about 0.4V in fact).

The problem was when I tried the SD103C, which is what I'd intended to use. It seemed to work okay. But then I tried removing the pullup, just to see if there was any voltage 'getting through' the diode. Without the pullup, and with the control line high, I was seeing 2V. Essentially this:



Is that a problem or just an artefact of measuring a somewhat artificial situation?

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That's a very important detail. Without the pull-up, and with the CPLD output high, you've got the very low reverse leakage current of the diode feeding into the very high input impedance of the RAM and your meter. The product of these will be some voltage, but it won't be easy to accurately predict what it is. But that's OK, because it isn't important. Nothing depends on that voltage. You won't be trying to run the system without the pull-up.

Still, I would also prefer to do all this in logic. Those resistors are going to slow things down. If you can find three unused inputs on the CPLD for configuration switches, there's no need for them.

You need at least one CPLD output pulling down if you hope to get a logic low.

(I think, once you introduce diodes, you probably need to be thinking of currents as well as voltages.)

(I think we saw someone before who was working on the mistaken assumption that you'd get a zero if nothing was driving a one.)

I suppose I have been thinking in terms of the CPLD_CE outputs being either 5V or 0V. But is it possible to switch them between 0V and High-Z?

Otherwise, I'm not sure how this would be done in logic. I'm already using decoding logic to choose between the five outputs (one low, the other high depending on the setting of an internal register). If an output 0-3 is selected, that either enables the ROM of the same number or the RAM chip, depending on the jumper setting. If CE4 is selected, it enables the RAM.

BTW, this is a 1MHz system, so speed is not of the essence.

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It might be, but that is not the solution unless it's your only option. Again, you might want to toss the diodes and try setting the CPLD outputs to "open drain". Or if for some reason that is not a possibility with your CPLD, then use buffers that have open drain outputs. There will be no short since in open drain mode they will not supply any power, just pull thing low. The pull-up will pull the /CE lines high when the CPLD is not pulling them low.

The spec sheet of that diode says it can have a reverse leakage of up to 5uA. If you have the pull-up removed, you could easily see 2V with that reverse current driving a single CMOS input alone.

I would really look into the open drain option.

EDIT: A hi 'Z' mode would also work too, on further reflection. And you could still loose the diodes.

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Bill

Yes, that's not a problem. Basically, one of the five outputs will be low in order to select the appropriate chip. It's also valid for them all to be high - ie, when I'm not addressing these devices at all. I'm not assuming anything is going to be low - it's the job of one of the outputs going low to create that situation. In the absence of that, all lines will be high due to the pullups.

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> I suppose I have been thinking in terms of the CPLD_CE outputs being either 5V or 0V. But is it possible to switch them between 0V and High-Z?

That's what open drain is!

I'm using the ATF1502AS. The datasheet mentions an optional 'open collector' mode for the I/O pins, but leaves it at that. No mention of how you achieve this.

Starting to think I'm out of my depth with this one and I might go for a simpler board first that just has the RAM without the complication of the ROMs.

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open drain and open collector are more or less the same for these purposes - you can drive a zero, or not drive.

You have logic to produce four /CE signals, and you're using external circuitry to steer them to different chips (and in the case of the RAM, to combine several of them) depending on a user-defined configuration. I'm suggesting to move the steering into the CPLD, and the configuration to CPLD inputs.

if I've got the logic right. Something like that. If an input is 0, the corresponding ROM is selected for that address range. If the input is 1, RAM is selected.

That's assuming you have four spare CPLD inputs, of course. And the CPLD is able to fit the extra logic.

Use an intermediary value for the particular chip select .. say CS3 .. and call it CS3i then, where CS3out is the actual chip select pin, in VHDL you'd write:



This means when CS3i is high it will put pin CS3out into hi-impedance mode (open the collector/drain - disconnect it from Vcc or any internal pull-up circuitry) and when CS3i is low it will drive CS3out low.

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