6502.org Forum  Projects  Code  Documents  Tools  Forum
It is currently Thu Mar 28, 2024 11:32 pm

All times are UTC




Post new topic Reply to topic  [ 30 posts ]  Go to page 1, 2  Next
Author Message
PostPosted: Mon Dec 04, 2023 12:33 pm 
Offline
User avatar

Joined: Fri Nov 09, 2012 5:54 pm
Posts: 1387
//Previos thread: 8364R7 Amiga Paula dissection.

This thread is about a transistor level dissection of the Rockwell R6545 CRTC (CRT controller),
brought to you by Frank Wolf and ttlworks.

In the beginning, there was the Motorola MC6845 CRTC,
and back then it was quite the thing for displaying text and graphics.
//Hitachi had the HD46505.
//During the cold war time, CM607 was a Bulgarian MC6845 clone.

The MC6845 even was used in early graphics cards for the IBM PC: MDA, HGC, CGA...
So as long as there are IBM compatible PCs which happen to have graphics cards
we can expect that there is something either in the hardware or at least in the software
which convincingly can emulate a MC6845, but I'm getting off topic.

The 6545 was intended to be a compatible drop in replacemend for the MC6845, featuring some additional functionality.
And that's where trouble starts: there were 6545 chips from different vendors, adding _different_ functionality.
André Fachat has a nice overview about the differences
and about the CRTC internals.

;---

From the list of features, to us the Rockwell R6545 was the most interesting 6545 variant,
because it offered things like interlaced mode and horizontal scrolling.

Metal traces in the R6545R1 chip looked like they were tacked together by an intern
on Monday morning before he had his first cup of coffee,
so the vectorisation of the silicon took Frank a bit longer than usual.

Note:
The circuitry inside the R6545 which is driven by CCLK uses dynamic latches,
so you better make sure that CCLK doesn't go slower than maybe 2kHz
(what should not happen in a typical application).
But this and the limited address range makes the R6545 a really bad choice
if you are in seek of a DMA chip for playing audio samples...

Note:
For consistence with Frank's notation, low_active signals are named foo#, not /foo.

Orientation for all the chip pictures: MA7 pad is North.

;---

Datasheets:
Bitsavers: Motorola MC6845 datasheet
Bitsavers: Motorola AN-0851 "MC6545 simplifies video display controllers", 1981
Bitsavers: Motorola AN-0834 "using the MC68000 and the MC6845 for a color graphics system", 1981

MOS 6545-1 CRTC controller datasheet, Nov. 1981
MOS 6545-1 CRTC controller datasheet, recreated

Rockwell R6545-1 CRTC datasheet, Dec. 1980

Bitsavers: Synertek 1981-1982 data catalog:
SY6545, page 3-139, PDF page 238
SY6545-1, page 3-155, PDF page 254

CRT controller handbook, Gerry Kane, 1980

Attachment:
R6545E.pdf [1.04 MiB]
Downloaded 32 times


Top
 Profile  
Reply with quote  
PostPosted: Mon Dec 04, 2023 12:33 pm 
Offline
User avatar

Joined: Fri Nov 09, 2012 5:54 pm
Posts: 1387
Eagle 6.4 schematics for my schematic pictures in this thread,
just in case if somebody needs them.

Note: KiCad is supposed to be able to import these schematics,
unfortunately it doesn't seem to be possible to disable the layers 'name' and 'value' in KiCad schematics,
so making my schematics look nice and clean in KiCad will require some work, sorry.

Attachment:
r6545r1__dissect_schematics.zip [1.13 MiB]
Downloaded 29 times


Top
 Profile  
Reply with quote  
PostPosted: Mon Dec 04, 2023 12:36 pm 
Offline
User avatar

Joined: Fri Nov 09, 2012 5:54 pm
Posts: 1387
A picture of the R6545R1 silicon, with the interesting areas marked according to the cheat sheet.

Attachment:
r6545r1_orientation.png
r6545r1_orientation.png [ 94.69 KiB | Viewed 9395 times ]


Just as a reference, another picture of the R6545R1 silicon without the markings.

Attachment:
r6545r1_small.png
r6545r1_small.png [ 426.54 KiB | Viewed 9395 times ]


Microscopic picture of the R6545R1 silicon:

Attachment:
si_r6545r1.jpg
si_r6545r1.jpg [ 5.09 MiB | Viewed 9395 times ]


Top
 Profile  
Reply with quote  
PostPosted: Mon Dec 04, 2023 12:37 pm 
Offline
User avatar

Joined: Fri Nov 09, 2012 5:54 pm
Posts: 1387
R6545R1 cheatsheet:

Attachment:
r6545r1_0_cheatsheet.png
r6545r1_0_cheatsheet.png [ 516.75 KiB | Viewed 9395 times ]


Actually, the cheatsheet above was the second try.
The first try didn't work out well:

Attachment:
r6545r1_0_old_cheatsheet.png
r6545r1_0_old_cheatsheet.png [ 727.35 KiB | Viewed 9395 times ]


Top
 Profile  
Reply with quote  
PostPosted: Mon Dec 04, 2023 12:40 pm 
Offline
User avatar

Joined: Fri Nov 09, 2012 5:54 pm
Posts: 1387
First:
sorry that we lack the capacity for interpreting the results of the dissection,
also we lack the capacity for writing the usual detailed text.

From our experience, best practice for dissecting a peripheral chip
is to do the pads (plus their drivers) first,
then to go for clock generation and reset
(because clock and reset signals will be used all over the chip),
and then to dissect the bus interface plus the address decoder.

Once you have the address decoder, you can tell which of the register Bits
inside the chip goes where.
And then to go for "the rest" between the register Bits and the pads.

;---

1abcdeh)

So now some pads:

Attachment:
r6545r1_1abcdeh_some_pads.png
r6545r1_1abcdeh_some_pads.png [ 101.54 KiB | Viewed 9395 times ]


Attachment:
si_r6545r1_1a_cr4_ma12.png
si_r6545r1_1a_cr4_ma12.png [ 24.3 KiB | Viewed 9395 times ]

Attachment:
si_r6545r1_1b_ma_mux.png
si_r6545r1_1b_ma_mux.png [ 10.5 KiB | Viewed 9395 times ]

Attachment:
si_r6545r1_1c_ap_inverter.png
si_r6545r1_1c_ap_inverter.png [ 8.24 KiB | Viewed 9395 times ]

Attachment:
si_r6545r1_1d_cclk.png
si_r6545r1_1d_cclk.png [ 15.2 KiB | Viewed 9395 times ]

Attachment:
si_r6545r1_1e_d7.png
si_r6545r1_1e_d7.png [ 29.72 KiB | Viewed 9395 times ]

Attachment:
si_r6545r1_1h_a_p_inverter.png
si_r6545r1_1h_a_p_inverter.png [ 9.36 KiB | Viewed 9395 times ]


Top
 Profile  
Reply with quote  
PostPosted: Mon Dec 04, 2023 12:42 pm 
Offline
User avatar

Joined: Fri Nov 09, 2012 5:54 pm
Posts: 1387
1f) RA0
1g) RA4

These pads have a little bit more of logic attached to them:

Attachment:
r6545r1_1fg_ra0_ra4.png
r6545r1_1fg_ra0_ra4.png [ 64.35 KiB | Viewed 9393 times ]


Attachment:
si_r6545r1_1f_ra0.png
si_r6545r1_1f_ra0.png [ 46.77 KiB | Viewed 9393 times ]

Attachment:
si_r6545r1_1g_ra4.png
si_r6545r1_1g_ra4.png [ 28.58 KiB | Viewed 9393 times ]


;---

1i) MA multiplexer control

The edge detector for the light pen also had ended up in there,
we somehow had to cut that chip into pieces,
and it isn't always obvious which part does what...

Attachment:
r6545r1_1i_ma_mux_control.png
r6545r1_1i_ma_mux_control.png [ 46.19 KiB | Viewed 9393 times ]


Attachment:
si_r6545r1_1i_ma_mux_control.png
si_r6545r1_1i_ma_mux_control.png [ 45.54 KiB | Viewed 9393 times ]


Top
 Profile  
Reply with quote  
PostPosted: Mon Dec 04, 2023 12:43 pm 
Offline
User avatar

Joined: Fri Nov 09, 2012 5:54 pm
Posts: 1387
2) CCLK clock generator

CCLK character timing clock is the time base for all of the counters.

We have the usual clock generator built around a RS flipflop.
RS flipflop basically is built from two NOR gates.

Attachment:
r6545r1_2_cclk.png
r6545r1_2_cclk.png [ 33.26 KiB | Viewed 9393 times ]


Attachment:
si_r6545r1_2_cclk.png
si_r6545r1_2_cclk.png [ 58.93 KiB | Viewed 9393 times ]


Top
 Profile  
Reply with quote  
PostPosted: Mon Dec 04, 2023 12:44 pm 
Offline
User avatar

Joined: Fri Nov 09, 2012 5:54 pm
Posts: 1387
3) R/W#, PHI2, RS, CS#

Now for a closer look at the logic which is attached
to the R/W#, PHI2, RS, CS# pads:

Attachment:
r6545r1_3_rw_phi2_rs_cs.png
r6545r1_3_rw_phi2_rs_cs.png [ 80.43 KiB | Viewed 9393 times ]


Attachment:
si_r6545r1_3_rw_phi2_rs_cs.png
si_r6545r1_3_rw_phi2_rs_cs.png [ 74.42 KiB | Viewed 9393 times ]


Top
 Profile  
Reply with quote  
PostPosted: Mon Dec 04, 2023 12:45 pm 
Offline
User avatar

Joined: Fri Nov 09, 2012 5:54 pm
Posts: 1387
4) read write logic

It is attached to 3), and it decides whether there is:
generic register read, generic register write,
status register read, address register write.

Attachment:
r6545r1_4_read_write.png
r6545r1_4_read_write.png [ 119.26 KiB | Viewed 9393 times ]


Attachment:
si_r6545r1_4_read_write.png
si_r6545r1_4_read_write.png [ 46.33 KiB | Viewed 9393 times ]


Top
 Profile  
Reply with quote  
PostPosted: Mon Dec 04, 2023 12:47 pm 
Offline
User avatar

Joined: Fri Nov 09, 2012 5:54 pm
Posts: 1387
5a) address register
5b) address decoder

The address register basically is a 5 Bit half_static transparent latch,
attached to the North end of the address decoder.

The address decoder then selects a generic register to be read/written.

Attachment:
r6545r1_5ab_address_decoder.png
r6545r1_5ab_address_decoder.png [ 90.42 KiB | Viewed 9393 times ]


Attachment:
si_r6545r1_5a_a4.png
si_r6545r1_5a_a4.png [ 12.03 KiB | Viewed 9393 times ]

Attachment:
si_r6545r1_5b_address_decoder.png
si_r6545r1_5b_address_decoder.png [ 134.5 KiB | Viewed 9393 times ]


Top
 Profile  
Reply with quote  
PostPosted: Mon Dec 04, 2023 12:48 pm 
Offline
User avatar

Joined: Fri Nov 09, 2012 5:54 pm
Posts: 1387
6) RST#, LPEN input

//The TEST pad is not available outside the chip.

RST# resets the counters in the chip.
Note, that RST# works a bit different from the reset input we had in the previous 65xx chips:
it is intended to synchronize the 6545 frame timing with line frequency,
or with "a master 6545" for implementing split screen and such.

LPEN is the light pen input.

Note:
LPEN input active blocks RES#.
RES# input active blocks light pen detection.

Attachment:
r6545r1_6_rst_lpen_input.png
r6545r1_6_rst_lpen_input.png [ 75.58 KiB | Viewed 9393 times ]


Attachment:
si_r6545r1_6_rst_lpen_input.png
si_r6545r1_6_rst_lpen_input.png [ 76.75 KiB | Viewed 9393 times ]


Top
 Profile  
Reply with quote  
PostPosted: Mon Dec 04, 2023 12:49 pm 
Offline
User avatar

Joined: Fri Nov 09, 2012 5:54 pm
Posts: 1387
7) VSYNC output and logic

Attachment:
r6545r1_7_vsync_output.png
r6545r1_7_vsync_output.png [ 128.15 KiB | Viewed 9393 times ]


Attachment:
si_r6545_7_vsync_output.png
si_r6545_7_vsync_output.png [ 86.95 KiB | Viewed 9393 times ]


Top
 Profile  
Reply with quote  
PostPosted: Mon Dec 04, 2023 12:50 pm 
Offline
User avatar

Joined: Fri Nov 09, 2012 5:54 pm
Posts: 1387
8) CRSR, DEN output

CRSR (cursor active) and DEN (display enable) outputs
can be delayed by one CCLK cycle,
and the implementation for the delay is quite minimalistic:

Attachment:
r6545r1_8_crsr_den_output.png
r6545r1_8_crsr_den_output.png [ 24.63 KiB | Viewed 9393 times ]


Attachment:
si_r6545r1_8_den_crsr_output.png
si_r6545r1_8_den_crsr_output.png [ 32.81 KiB | Viewed 9393 times ]


Last edited by ttlworks on Mon Dec 04, 2023 1:00 pm, edited 1 time in total.

Top
 Profile  
Reply with quote  
PostPosted: Mon Dec 04, 2023 12:53 pm 
Offline
User avatar

Joined: Fri Nov 09, 2012 5:54 pm
Posts: 1387
9) AP counter and logic

Unlike all of the other 6545 variants,
the Rockwell R6545 features an additional counter for CPU display memory access,
which basically can be incremented by register 31 reads/writes.

To me it looks like something like a kludge,
added to the 6545 circuitry by Rockwell,
note that additional clock generator.

//Since MA (memory address) already was taken,
//I had named that counter AP (address pointer).

Attachment:
r6545r1_9_address_pointer.png
r6545r1_9_address_pointer.png [ 58.06 KiB | Viewed 9392 times ]

;---

Attachment:
r6545r1_9ab_apl_counter_plus_logic.png
r6545r1_9ab_apl_counter_plus_logic.png [ 238.52 KiB | Viewed 9392 times ]


Attachment:
si_r6545r1_9a_apl_counter.png
si_r6545r1_9a_apl_counter.png [ 25.85 KiB | Viewed 9392 times ]

Attachment:
si_r6545r1_9b_apl_logic.png
si_r6545r1_9b_apl_logic.png [ 108.73 KiB | Viewed 9392 times ]

;---
Attachment:
r6545r1_9cde_aph_counter plus logic.png
r6545r1_9cde_aph_counter plus logic.png [ 189.86 KiB | Viewed 9392 times ]


Attachment:
si_r6545r1_9c_aph_counter.png
si_r6545r1_9c_aph_counter.png [ 23.38 KiB | Viewed 9392 times ]

Attachment:
si_r6545r1_9c_aph_inverter.png
si_r6545r1_9c_aph_inverter.png [ 9.65 KiB | Viewed 9392 times ]

Attachment:
si_r6545r1_9d_aph_carry.png
si_r6545r1_9d_aph_carry.png [ 24.02 KiB | Viewed 9392 times ]

Attachment:
si_r6545r1_9e_ap_control.png
si_r6545r1_9e_ap_control.png [ 41.3 KiB | Viewed 9392 times ]


Top
 Profile  
Reply with quote  
PostPosted: Mon Dec 04, 2023 12:55 pm 
Offline
User avatar

Joined: Fri Nov 09, 2012 5:54 pm
Posts: 1387
10a) register 0 //horizontal total
10b) register 1 //horizontal displayed
10c) register 2 //horizontal SYNC position

Attachment:
r6545r1_10abc_reg0_reg1_reg2.png
r6545r1_10abc_reg0_reg1_reg2.png [ 104.9 KiB | Viewed 9392 times ]


Attachment:
si_r6545r1_10abc_inverter.png
si_r6545r1_10abc_inverter.png [ 15.13 KiB | Viewed 9392 times ]

Attachment:
si_r6545r1_10abc_pullup.png
si_r6545r1_10abc_pullup.png [ 18.15 KiB | Viewed 9392 times ]

Attachment:
si_r6545r1_10abc_reg0_reg1_reg2.png
si_r6545r1_10abc_reg0_reg1_reg2.png [ 29.16 KiB | Viewed 9392 times ]


Top
 Profile  
Reply with quote  
Display posts from previous:  Sort by  
Post new topic Reply to topic  [ 30 posts ]  Go to page 1, 2  Next

All times are UTC


Who is online

Users browsing this forum: No registered users and 4 guests


You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to: