Well, I have a starting point for that, if you want one. It already has the data lines demultiplexed:

https://github.com/jmstein7/soft_65c816_core_SoC_23LC512

All you'd have to do is demultiplex the address lines, and, voilà, Bob's your Uncle! (And Fannie's your Aunt!)

Go! Make it a reality

Jon

thanks for the offer, but that 65C816 core still seems to have an 8-bit Data bus though. (or i'm reading VHDL wrong... i'm not sure, i've only ever used Verilog)

what i meant is a true 16-bit Data Bus, like the 8086 compared to the 8088, or the 68000 compared to the 68008.
which is a lot more tedious than just hooking up an existing 65816 to an external 16-bit bus. i basically have to build it from scratch.
For example instructions that are 2 or 4 bytes long take a different amount of cycles to fetch depending on if they are located at an even or odd address.
Same with accessing 16-bit words from Memory. aligned accesses would be 1 cycle long, but unaligned would take 2 cycles.

Lol, I said the data lines were demultiplexed, as in from the bank lines. But, I understand about Verilog - I only use VHDL when I'm forced to. I'd use Verilog all day long, if I could, over VHDL.

Back to the point; I was going to break-out the upper data lines and the bank lines, and I discovered that it's harder thank it looks. Also, I started using the 65C265, which has all the address lines available externally. I've also gone through the pains of making the 'C265 more user-friendly, by hardware and software.

http://forum.6502.org/viewtopic.php?f=4&t=7068

Jonathan