If you can convince me that
memory needs protection from dummy cycles then that would be a game changer. Maybe such a memory exists and I just haven't heard about it yet. But certainly the memory you and I use
doesn't need protection from dummy cycles, and WDC's over-eager recommendation doesn't apply -- our only concern is I/O. It's worth reviewing what's stated
above. Per the Truth Table, the I/O device will be enabled during data accesses but disabled during dead cycles, and that's all the protection from dead cycles we require.
To be clear: if memory doesn't need protection from dead cycles then VPA is useless for that purpose (although VPA does have other purposes).
Quote:
Something you may be overlooking is that a spurious ROM or I/O chip select may be inadvertently associated with an unwanted wait-state.
Oops, yes; I did overlook that. So let's look at using VPA for the purpose of avoiding needless wait states.
If someone uses a Wait State Generator with ROM it'll be to reconcile the use of the (slow) ROM with the goal of higher clock speeds and better overall performance. Of course the fastest solution of all would be to eliminate routine ROM accesses entirely, either by copying ROM to RAM upon powerup or by initializing RAM with a microcontroller or by other means. These topics are discussed elsewhere on the forum. But circumstances and preferences vary, and some will find the ROM + WSG combination appealing.
In the context of the ROM + WSG combination, I/O is easy to deal with because VDA=1 is the only condition that indicates I/O will need a Wait State. But ROM is less easy because unlike I/O it may contain both code and data; thus VDA=1 and VPA=1 are
both conditions that indicate RAM needs a WS. In other words, bringing ROM into the Wait State picture is what brings VPA into the picture.
The prop delay from bringing VPA into the WS picture results in a tradeoff. Skipping unneeded wait states is definitely good news for ROM operations, but due to added prop delay the system as a whole (RAM, ROM, I/O) will have a somewhat lower ceiling on clock speed. The question arises, does a lot of your activity depend on ROM? Stack and Z-pg will always be a pretty big slice of the pie.
And how much will the clock ceiling be lowered? Quite bit, if the glue logic is build with discrete chips. A CPLD will shrink this impact, although I'd hesitate to call it vanishingly small -- we'd need to quantify that by determining the delay resulting from an extra pass internally through the CPLD's logic array. This'll be less than but on the same order as the device's pin-to-pin delay.
Speaking of pins, another cost to be justified is the CPLD pin used to input VPA to the device. I'm not saying it'll never be worth it -- only pointing out that ignoring VPA (and suffering unneeded ROM wait states) may well open the door to a better use for that pin. Or, perhaps the reduced pin requirement will allow the user to downsize from a big CPLD to a small one, or switch to some other type of PLD entirely.
At the risk of becoming (even more) tiresome,
I'll set aside the WSG topic and return briefly to the issue of dead cycle protection. And the pivotal question is, does memory needs protection from dead cycles? If the answer is no then our only concern is I/O. And the Truth Table and diagram I posted plainly show how I/O can be protected using VDA alone.
-- Jeff
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