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banedon
PostPosted: Mon Apr 18, 2022 1:28 pm 
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Hi guys

I've working on a memory board redesign circuit which makes use of a signal derived from a 2 MHz NMOS 6502's RWB signal.
I need to have a way for the operator to disable the ability to write without introducing a prop delay on the RWB signal itself (otherwise I'd just an OR gate or similar).
Here's what I've come up with (see below).
Q1 should remove the prop delay between R/W in and R/W out when R/W transits high-low or low-high.
IC1 inverts SW1 using a Schmitt trigger, so deals with debouncing (along with R1 & C1).
R2 serves to pull R/W out up if Q1 is not enabled. Not sure if the value of 3K3 is suitable though?

Attachment:
6502 RWB switch.JPG
6502 RWB switch.JPG [ 42.09 KiB | Viewed 484 times ]


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gbm
PostPosted: Mon Apr 18, 2022 1:51 pm 
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And why don't you replace the transistor with a jumper?
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banedon
PostPosted: Mon Apr 18, 2022 1:56 pm 
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gbm wrote:
And why don't you replace the transistor with a jumper?

The circuit needs to have the capability of being enabled/disabled from outside of the case with everything powered on and running.
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GARTHWILSON
PostPosted: Mon Apr 18, 2022 9:35 pm 
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Your BJT is not configured right for the application.  On the back of an envelope, I worked through a couple of different ways to do it, then decided you'd be much better off using an analog switch like a 74HC4066.

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banedon
PostPosted: Mon Apr 18, 2022 9:36 pm 
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If SW1 is not linked, everything is fine and RWB is held high.
However, if SW1 is linked, Q1 is enabled and RWB, although you can see it try to change, enever dips below 4v for lows and 4.5v for highs/
Tried 2K2 to 4K4 pullup for R2 - makes no difference.
From what I can find out, fast signals should be ok with any resistor in this range, so it's a bit odd. Might be Q1 causing an issue?
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banedon
PostPosted: Mon Apr 18, 2022 9:38 pm 
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GARTHWILSON wrote:
Your BJT is not configured right for the application. On the back of an envelope, I worked through a couple of different ways to do it, then decided you'd be much better off using an analog switch like a 74HC4066.

Hi Garth
Is it that Q1 isn't current limited which is causing the issue? Can you advise how it's misconfigured?
In the meantime, I'll take a look at 74HC4066, although I might not able to used it as the PCB real estate cannot be expanded and there's virtually none left. Might be ok if I lose the inverter.
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GARTHWILSON
PostPosted: Mon Apr 18, 2022 10:10 pm 
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banedon wrote:
GARTHWILSON wrote:
Your BJT is not configured right for the application.  On the back of an envelope, I worked through a couple of different ways to do it, then decided you'd be much better off using an analog switch like a 74HC4066.

Is it that Q1 isn't current limited which is causing the issue? Can you advise how it's misconfigured?

To get an NPN transistor to conduct, the base has to be pulled above the voltage of the emitter (and the collector voltage also needs to be above the emitter voltage—with a special-case millivolt exception I won't get into here).  I'll speak here in terms of electron flow, not conventional current.  Electrons flow from the lower voltage to the higher voltage.  The electrons will flow into the emitter and out the base.  Since your emitter is pulled up to Vcc, and the base can't go above that, it won't conduct.  You might get some slight coupling from collector to emitter due to parasitic capacitance, but not what you want.  As the base gets pulled above the emitter, the V/I curve of the BE junction means you'll need to limit the base current with a resistor in most situations—if indeed you were biasing it so you could get any current.  Remember that BJTs are current-controlled devices, whereas FETs are voltage-controlled.  (Note also that when biased in the opposite direction, ie, base voltage below the emitter voltage, the breakdown voltage is usually around 5V.)  Then conducting, electrons can flow into the emitter and out the collector to the higher voltage.  The ratio of collector current to base current is the beta.  So for example, if you pull 100µA from the base, and have a beta of 200, you can get 20mA out the collector before the VCE (collector-emitter voltage) rises.  Up to that point, the transistor is saturated, and the voltage across it will be just the current times the internal emitter resistance.  That's the generality.  The reality is a little more complicated, but you can get the details in the curves given in the data sheet, where of course the "elbows" won't be perfectly sharp, and the "horizontal" parts won't be perfectly horizontal, and the saturation portion won't be perfectly vertical.  In any case, you can't have the NPN's collector pull the emitter down.

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banedon
PostPosted: Mon Apr 18, 2022 11:26 pm 
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Many thanks for explaining and I think I understand (at least enough to see why my circuit doesn't work).
I've also been looking at MOSFETS. So far, from what I undestand (and I might be wrong), the enable/disable would connect to the Gate, the Source the ground and Drain to the load. Otherwise, we need a much higher voltage that the RWB line - as that runs close to VCC when high, not possible.
I.e. similar to the BJT, from what I picked up from yuor explanation.
Having the load before the MOSFET isn't really do-able for RAM, which leaves us back with you original recommendation: 74HCT4066
Unfortunately, I have no additional PCB space to cram another IC in unless I do a big redesign, so it looks like I might have to ditch this switch option. I'll have a think on it when my brain isn't quite so tired.
Thanks for you help with this - appreciated :)
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SpaceCoaster
PostPosted: Tue Apr 19, 2022 3:25 pm 
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Single channel versions of analog switches are available. Surface mount but not crazy small so not much larger than a BJT.

For instance M74VHC1GT66DFT2G and many others https://mou.sr/3KSr3si
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