Direct page addressing incurs a one cycle penalty (when the direct page is not pointing to a physical page boundary) because the direct page offset has to be added to the direct page register in order to compute the effective address instead of simply concatenating the offset to the high byte of the DP register when the low byte is zero.

Why doesn't stack relative addressing also incur a one cycle penalty when the stack pointer is not pointing to a physical page boundary?

i would assume because the stack always has that extra cycle pentalty as adding extra circuitry to skip some part of the stack address calculation wouldn't be worth it for the 1/256 chance that the stack happens to be on a page boundary.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

That does make a lot of sense. Say, does anyone know how to get involved with the visual6502 project? I'd be very interested in a visual65816 to help get answers to some of these hardware questions.

I recently noticed that you can even overflow or underflow the stack and the processor just keeps going, which makes it difficult to debug trashing the stack. A warning on this condition is something I'd like to see added to emulators.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

The visual6502 project is more or less done at this point, I think. The code base is open, and there are various forks, and various people continue to reverse-engineer chips and to extend the simulator, but the core team are not really active any more. A sign of this is that the wiki is broken and has been for a while - we refer people to the archive instead. The necessary techniques for making a visual65816 are all known, but it will take effort, and as yet, as far as I know, no-one has done it.

Well you can put my name down as one of the people who are interested in helping, but after the first version of this 65816 compiler I'm working on is ready.

65816 legacy behavior always matches or betters 65C02. Exotic behavior may not match or better 65C02.

I would say no one would use 65816 if that were not the case, however we have some very peculiar members on the 6502 Forum who would probably use it for convenience rather than speed (which is approximately zero, nowadays). A good counter-example is Intel's Pentium4 which failed to match clock cycles of its predecessor. It runs contemporary GCC output very well but, at launch, some new and old software ran slower.

Actually, adding pointers is a subject of architectural improvement because it requires O(n log n) transistors to add n bits with the least delay. We also have the case where (d,S),Y addressing mode may require adding 16 bit stack pointer to 16 bit RegY and 8 bit immediate value. That is five 8 bit addition operations. One addition can be overlapped with operand fetch and one addition can be eliminated if DP is page aligned.

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Modules | Processors | Boards | Boxes | Beep, Beep! I'm a sheep!