Hi guys,

Running into a bit of an issue with one of my designs. I'm using an LSF0102 to translate between 3.3v and 5v. It's an open collector translator and is supposed to do bidirectional translation, but I can't get it to uptranslate to 5v, it will only output ~3v on the 5v side (b).

Currently running a Nexperia LSF0102DP since my preferred TI LSF0102DCUR is out of stock. Below is a snip of my schematic, I'm not seeing anything wrong, am I misunderstanding the datasheet?

What does the 5v side connect to? If you haven't already, you could try a test with no load attached. In other words, disconnect the level-shifter circuit from whatever logic you intended to drive. There would be no load other than the 'scope or multimeter you're using to measure the voltage.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

The 5v side connects to a 6522, 6502, and an ATF1508, the 3.3v side only connects to a 3.3v pin on a Mercury II fpga.

The idea behind the circuit was to allow for a clock on the 5v side to be present and down translate to 3.3v to a clock pin on the FPGA, or to allow the fpga to drive the clock line and up convert to 5v on the CPU side.

I did note when allowing the output of the FPGA to float resulting in A1 being pulled up by the resistor I did get a 5v output on the B1 pin. So something about driving A2 to 3.3 is locking B2 to 3.3, but when A2 is allowed to float and pull up to 3.3 then B2 pulls up to 5v. I was trying to set the output of the fpga to Z when clock is high and to 0 when low, but it doesn't seem to want to cooperate. I may fuss a little more with it later.

For what it's worth, I notice TI has a series of videos dealing specifically with these products.

voltage-level-translation-lsf-family

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

As of the last update I thought the open drain output wasn't working on the FPGA, but it turns out it was, the pullup on the 5v side just wasn't nearly strong enough. I've since replace the 10k with a 220 on the 5v side and it is pulling up to just over 4 volts and working. Lowering the resistance of the pullup on the 3.3v side just increased the voltage at 0 logic on the 5v side. I fear having a 200ish ohm resistor on the 5v side, while works when driving the line from the 3.3v side, will be more current (25ish ma) than the oscillator can sink if I choose to drive the line from the 5v side instead of the FPGA. I'll have to test it later, or at least read the oscillator data sheet.