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PostPosted: Sun Sep 05, 2021 1:23 am 
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So, based on a recent post and finding some odd issues with certain CF Cards, I decided to start a new thread on this topic.

Background: My C02 Pocket SBC is a 6 MHz W65C02 with 32KB RAM/ROM and a NXP SCC2691 UART. It uses an Atmel AT22V10CQZ single glue chip for address decoding for RAM/RAM, I/O and qualified read and write signals. The PLD is rated at 20ns, which should be fine for a 6 MHz clock rate.

Add in my later designed adapter which adds a Maxim DS1511 RTC and an IDE interface with a 16-bit data port based on a pair of 74AC573 latches. It works fine... and I've managed a custom build of Richard Leary's DOS/65 running on it. However, I found certain CF Cards either wouldn't work at all or wouldn't work properly, but could never quite figure out the issue.... but never really dug deep into the issue either.

Next... moving to 3.3V, which is where this thread gets it's start from (viewtopic.php?f=4&t=6722#p86843)

Alliance discontinued the 70ns SRAM I used in the C02 Pocket, but they have a 55ns version, so picked up a few. Oddly, this RAM chip would not work in the C02 Pocket, simply dead on power up. While I was doing some initial testing to get a SC28L92 DUART in place of the SCC2691, I decided to swap out the PLD with an Atmel AT22V10C, which is rated at 15ns. I also have the 55ns SRAM in and connected the RTC/CF Card adapter and made a few minor changes to get DOS/65 running. I was also to kick the CPU clock up to 10 MHz without issue. Just for giggles, I decided to pop in the other CF Cards that never worked before and found that they worked perfectly fine... hence the decision to investigate more and create this thread.

In short, just swapping out the ATF22V10CQZ (which is rated at 20ns) to the ATF22V10C (rated at 15ns) allowed both the 55ns Alliance SRAM to function "and" the other Compact Flash cards which didn't before... hence the topic for this post. I've done some additional testing and it's consistent... the faster PLD timing resolves the issues for the non-working CF Cards found earlier and the recent perplexing find that the same SRAM part number with a 55ns (vs the older 70ns part) now working... who knew!

So, turns out that 5ns really can be a make or break in a 6 MHz system. I also dropped the clock rate to 4 MHz and it still didn't work with the 55ns SRAM part. So I have to believe that it's more than the 5ns timing spec difference. In any case, I'll be swapping out all of ATF-xxxxx-CQZ parts for standard ones.

Not sure if anyone else has fallen into some odd hardware issues using PLDs, but figured this was worth posting, mostly as an FYI, hope it helps someone.

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PostPosted: Sun Sep 05, 2021 5:35 am 
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I'm finding it a little hard to believe that the 20ns GAL was your problem. I've run my POC V1.2 at 20 Mhz, and that is with all-discrete logic. That logic is barely faster that your GAL. I think something else is at work here.

BTW, could you please post the code you used to program the GAL?

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PostPosted: Sun Sep 05, 2021 8:40 am 
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Is there a possibility that your glue logic can cause a glitch on some output, and a slightly faster part produces no glitch, or possibly a glitch too short to cause a malfunction?


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PostPosted: Sun Sep 05, 2021 11:25 am 
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The two problem areas I've observed regarding compact flash implementation in retrocomputing are:
1. Insufficient setup time from Address-and-chip-select valid to read or write strobe asserted. The spec calls for 25nS setup, but some CF disks can tolerate 0nS; few can even tolerate negative setup time. Smaller the setup time, fewer brands of CF will work.
2. Data-dependent noise that affects the CF read strobe and causes spurious read of CF data FIFO resulting in data loss.

Issue 1 can be determined by looking at the decoding logic of CF interface. Issue 2 is PC board layout dependent, but source terminating resistors for data lines and noise filter for CF read strobe are helpful.
Bill


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PostPosted: Sun Sep 05, 2021 5:06 pm 
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The "zero power" features of the CQZ version might also be worth investigating. Could possibly be those, rather than the difference in speed rating?


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PostPosted: Sun Sep 05, 2021 5:25 pm 
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First, thanks for all of the replies.... it is an interesting problem.

It's seems more basic related to the CQZ version of the PLD... if I only have the base Pocket SBC (no RTC/CF-Card adapter attached), there's still a problem. Swapping from the 70ns to 50ns Alliance memory fails, the SBC is dead. I've even tried several different Pocket SBC boards and several different 55ns SRAM chips... it's consistent, it always fails. Replace the CQZ version with the standard C version of the PLD and the problem goes away.

Here's the source for the PLD code. I've used this same source for the ATF750CL, the ATF22V10C and the ATF22V10CQZ. Only the CQZ chip has the issue, so I'm also thinking it likely is related to the "zero power" feature of that version.

Code:
Name     Glue3 ;
PartNo   01 ;
Date     10/31/2017 ;
Revision 01 ;
Designer KM ;
Company  Analogue Technologies ;
Assembly SBC2 ;
Location  ;
Device   g22v10 ;

/* *************** INPUT PINS *********************/
PIN 1    = CLK                       ; /*                                 */
PIN 2    = A15                       ; /*                                 */
PIN 3    = A14                       ; /*                                 */
PIN 4    = A13                       ; /*                                 */
PIN 5    = A12                       ; /*                                 */
PIN 6    = A11                       ; /*                                 */
PIN 7    = A10                       ; /*                                 */
PIN 8    = A9                        ; /*                                 */
PIN 9    = A8                        ; /*                                 */
PIN 10   = A7                        ; /*                                 */
PIN 11   = A6                        ; /*                                 */
PIN 13   = A5                        ; /*                                 */
PIN 23   = RW                        ; /*                                 */

/* *************** OUTPUT PINS *********************/
PIN 14   = !IO1                      ; /*                                 */
PIN 15   = !IO2                      ; /*                                 */
PIN 16   = !IO3                      ; /*                                 */
PIN 17   = !IO4                      ; /*                                 */
PIN 18   = !IO5                      ; /*                                 */
PIN 19   = !ROM                      ; /*                                 */
PIN 20   = !RAM                      ; /*                                 */
PIN 21   = !MWR                      ; /*                                 */
PIN 22   = !MRD                      ; /*                                 */

/** Declarations and Intermediate Variable Definitions  **/
FIELD ADDRESS = [A15..0];

RAM = ADDRESS:['h'0000..7FFF];
IO1 = ADDRESS:['h'FE00..FE1F];
IO2 = ADDRESS:['h'FE20..FE3F];
IO3 = ADDRESS:['h'FE40..FE5F];
IO4 = ADDRESS:['h'FE60..FE7F];
IO5 = ADDRESS:['h'FE80..FE9F];
ROM = ADDRESS:['h'8000..FDFF]
        # ADDRESS:['h'FEA0..FFFF];
/** Logic Equations **/
MWR = (CLK & !RW);
MRD = (CLK & RW);


Perhaps there is some code option in WinCUPL to compensate for the CQZ version, or the simple fact is, it shouldn't be used in this particular application for some odd reason.

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PostPosted: Sun Sep 05, 2021 6:04 pm 
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I'm not seeing anything remarkable in your CUPL code to explain this, in particular, no pin nodes to increase the overall prop time of the part. I looked at the Atmel data sheet and didn't see anything specific to the 'Q' part that would explain a loss of function in your application.

One thing to bear in mind is the output of your GAL is TTL-level, not CMOS. Those outputs are only guaranteed to reach 2.4 volts when at logic 1. That could be a factor.

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PostPosted: Sun Sep 05, 2021 11:26 pm 
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I found some other Atmel documentation regarding their PLDs... some interesting content regarding their "Z" (zero power) devices and selection of decoupling capacitors.

Attachment:
DOC0790.PDF [172.92 KiB]
Downloaded 64 times

Attachment:
doc0484.pdf [59.34 KiB]
Downloaded 49 times


Page 8 in the first doc talks to the "Z" devices and decoupling... and references the second doc for selecting caps. In short, they recommend a 0.22uF decoupling cap.

I'll try adding an additional cap on the PLD and see if it makes any difference. I've got over a dozen decoupling caps on the small PCB now, but only a single 0.1uF directly on every chip.

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