Hi guys

I'm trying to design a very compact, basic board for prototpying I/O.
The project will consists of :

Mainboard
Power rail at 5V
Clock & reset circuits
65816 cpu - planned 8MHz speed, higher if I can wangle it
1 to 16MB SRAM
12KB ROM
Glue logic CPLD
Upper 8bit address Latch

I would like to have all of the I/O run from a daughter board, so plan to run A0-15, D0-15, IRQ device inputs, I/O, Selects, PHI2, RWB, RESB, etc. all off of the board. The connector would be a pin header-to-edge connector or just pin header.
Given that it's not recommended to run buses directly off the board, I was wondering if it would work if I used transcievers - at least for the buses? I'm thinking the show-stopper might be the timings, but if I keep PHI2 low enough it might be fine?

Transciever allocation and direction
Address bus - uni directional outbound, 2 x 8 bit [edit: I might just make this A0-7 as I can't think of why A8-15 would be needed]
Data bus - bidirectional, 1 x 8 bit
I/O selects for VIAs, Serial, etc. - uni directional outbound, 1 x 8 bit
IRQ for VIAs, Serial etc. - uni directional inbound, 1 x 8 bit

Transciever
I'm currently looking at the TI SN74AC245. It has a 1 to 9ns delay across it A to B, B to A, /OE would be tied low (active) so no delay there.
The edge rise time says 8ns per volt which means potentially uyp to 40ns transition time of logic level change? Or am I getting that wrong?
If anyone knows of a better device then please let me know.

Designing
I'm going to design the project, post the circuit design here (not dealt with 65816's before so want the bus decoding checked) and then will have a PCB made. I would do it via wirewrap/point to point or breadboard, but the sockets for ww are expensive and I hate doing the latter two due to the number of connections involved.

Does the above sound feasible? If so, are there any gotchas I should look out for?

banedon:

I had a quick look-see at the data sheet for the 'AC245 you referenced above. Something in your statement did not seem right: The only dT/dV specification that I found in the data sheet on my quick read is the one referring to the input transition time. This means that for the part to operate correctly, circuits external to the part need to ensure that their outputs transition at rates exceeding 8ns/V. If signals with slower transition times are presented to the inputs of the 'AC245, the part may not operate correctly. For example, it may break into oscillation as the input signal slowly transitions through its input threshold voltage region.

The output transition rates of the part are not specifically identified. You should understand that the output transition times of this logic family are quite fast, and limited only by the load, primarily the load capacitance, that your design presents. In my experience, the output transition times for these advanced logic families would be difficult for you to measure with the typical test equipment we are able to afford as hobbyists.

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Michael A.

Hi Michael

Thanks for replying. I thought I might be misunderstanding it - many thanks for clearing that up .

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thanks for advising, Garth.
Part of my issue is PCB real estate and other is having the ability to just reconfigure I/O easily so i can have cards etc.
If I move the RAM and ROM to a daughter-board this will help with the former, but will not entirely work for the latter. I'll have a think on it, but I guess I'll most probably have to put the cards on the I/O pins of the VIAs.

Cheers again

Hi Bandeon, I've actually done exactly this for my "GameTank" project. The latest boards are a stack of two, with the processor on the bottom and audio/visual signal generated on the top. I'm still wrapping my head around the transmission effects I've largely conquered by happy accidents, but I did have one practicality note come to mind:

Using pin headers will become quite frustrating with that many lines as they deform a tiny amount with each disconnect. Initially it was easy but over time I had to start using a screwdriver to work them apart for inspection.

I'm a fan of the card edge connectors since I'm nostalgic for game cartridges, though they can take up a lot of space and require significant force.

A connector I've gotten great use out of for daughterboards is the TX24/TX25 connector from JAE. It's available in through-hole, is decently easy to solder, and the simple snap-in connection has been quite reliable. They also make it easier than with card edge connections to put the boards parallel, or make any guarantees about physical alignment.

Hi Agumander

Thanks for the heads up regarding the pin distortion and also the TX14/TX25 connectors. The ones I was looking at were these for edge connectors:
https://uk.farnell.com/amp-te-connectiv ... dp/2838988

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Yes, there are various benefits to isolating the data bus from the MPU. In your case, banedon, your intention is to attach a very large amount of RAM, which means a large amount of capacitance on the bus. It'll be better to let a transceiver -- not the CPU -- shoulder the burden of charging and discharging that load.

Also, remember that the MPU data bus is twice as "busy" as the demux'ed data bus downstream of a transceiver. That's because the MPU bus is driven to a different state on each phase. From the POV of your expansion bus, you'll greatly reduce challenges such as transmission-line effects if the expansion bus only carries the comparatively leisurely demux'ed data.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I'm working on a couple of 65c816 designs based of what you guys have said. This is the one which does as Garth suggestions and runs the memory off the board rather than the I/O. The other one I'll probably finish tomorrow which shows the I/O running of the board instead.
Please note this design is quite rough, but I think I've gotten it right for the most part, although I have a concern about the number of grounds and +5V lines in the RAM/ROM header (i.e. are there enough?). The PCB will be 4 layer: 1:signals, 2:gnd plane, 3:pwr plane, 4:signals.
Note that each VIA has two sets of pin headers: one for vertical and one for horzontal which can have a pin header-to-edge connector fitted.

[edit] I forgot to link the RWB_E on the RAM/ROM header - this will become RWB and the one next to it currently not used will become /RD.
I also have the issue, not previously considered ( ), that I need to qualify how the memory is mapped by the CPLD (ATF1504AS) as I now have a 24 bit address, with atleast the top 16 bits needing to be validated. What I might do is feed A15-A8 into the CPLD and have A23-A16 fed into another CPLD or GAL... Can anyone think of a better solution?

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Two each of Gnd and +5V ought to be sufficient, IMO. More would be somewhat better, but then you'd need a larger header.

You may also wish to be mindful of where the Gnd and +5V pins appear, as this has a bearing on AC performance. Just a reminder that every signal (eg A12, D4 etc) also causes current to flow in the Gnd and +5 lines in order to complete the circuit, and inductance is minimized when the signal has a return path that's physically nearby. Gnd and +5V are equally able to act as the return path. Whichever is closest will be the one that'll carry most of the current. (It's high-frequency AC that's at issue, not DC.)

So, the optimal strategy is to intersperse the 4 return lines among the signal lines rather than putting them at the ends of the header. The diagram below shows the general idea.

This isn't a matter that will make or break your design, so if you prefer a simpler arrangement that's OK. On the other hand, if you're aiming for faster clock rates and maximum performance then interleaved return paths absolutely deserve consideration.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Hi,

Hope it works out well - always good to have more '816 systems out there!

Mine "only" has 512KB of RAM, although I ought to be able to take it to 1MB without much difficulty (well, piggy-back chip soldering which I did for the 2 x 32KB chips on my 65C02 board) but really not sure what I'd use it for...

Re. your 12KB ROM - I treated bank 0 in mine like a BBC Micro, so 32KB RAM, 16KB "language" ROM, then 16KB OS (minus IO at $FExx) although it's really all RAM but that was the general idea. I can load BBC Basic into the language area at $8000 and run that in emulation mode, or my BCPL OS which runs in native 16-bit mode.

I have all that on a single board with 2 GALs for the address bus latch and address decoding (and some other little bits)

Cheers,

-Gordon

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--
Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

Thanks for looking at the circuit . I've gone through your points below with one or two questions:

1 & 2. Thanks for clarifying this. I've bnecome warey of using AC(T) due to warnings baout the high-low and low-high transitions speed causing ringing so have gotten into the habit of using HC(T)> i've modified the circuit.
3. Yep I forgot to reconnect that one . Have fixed that.
4. The symbol is a bit misleading (I need to redefine it). It's actually a bus resistor with each connection having it's own 3k3 resistor. If I have room I'll introduce 2 pin headers for RDY, NMY, BE which would allow room for them to be used as you suggest.
5. I've changed the note to reflect R14 is not optional/should be metal film if possible.
6. I'll add a SIP in as you recommend. Can you advise why this is needed?
7. The D input connects to both the /PHI2 line which is in turn connected to /Q of the same flip flop? This is for IC4A.
8. I hadn't added the memory decoding in yet as I was still considering my options on how to deal with the decoding. Would the CPLD be fast enough considering your comments about the need for speed that you emntion in 1) ?
9. The CPLD deals with IRQ arbitration, but as I may need to free up pins for I could move that to an AND gate IC (74HC21D). I'll also add a pull up for the Opendrain line which I forgt to add.
10. I'll add the recommended 2k2 SIP
11. JP3 is a stand in for a JTAG header, although not connected/realised yet. I will be adding one in properly.
12. I'll add a 3k3 to both RESB and the D1812

Hi Jeff

Thanks for the advice on this. I went for the current arrangement mostly to keep the number of pins down and also allow for me being a twit and plugging the card in the wrong way around - bus contention would occur, but nothing gets a dose of unrestricted +5V, etc. . On that note, I've been thinking about putting a detection circuit on the memory card which lights a red LED (green if the correct way) if you plug it in the wrong way or something similar. Or go down the keyed edge connector route.
Back to the power and gns: What I might do is still expand the header and add extra +5v and gnds while trying to still keep the above "you plugged it in wrong" system. Worst case, as you say, it can stay as-is.