drogon wrote:
One thing to note is that modern 65C22's (Specifically the more common W65C22S, but not the 'N' variant) are not designed to have their IRQ output be wire-or'd.
Ah, thanks for pointing that out. "S" is what I have in stock. So I will need to order some "N" versions to do an wire-or'd setup.
GARTHWILSON wrote:
I'm sure you mean open-drain versus totem-pole. As Jeff explained, open-drain and open-collector outputs do the same thing. They can only pull down; so if two or more outputs disagree, there's no contention. A totem-pole output OTOH can pull up as well as down. In the open-drain or open-collector situation, the only thing that can pull up is the pull-up resistor.
Yeah, I meant totem-pole. So from what I am gathering, totem-pole is much faster but more complex. Especially with adding additional components (AND) and possible contention. I assume the smarter move for me (at least for now) is to stick with the wire-or'd setup?
8BIT wrote:
You would read the IFR of each VIA and check bit 7 to see if it is set. If it is, then check the other bits to see what action caused the interrupt (Timer1, Timer2, CB1, CB2, Shift Register, CA1, or CA2).
If it's not set, then check the next device the same way.
AH! OK, this was the obvious bit I was missing. I was thinking the wiring/hardware was somehow telling the CPU which device interrupted it. But the reality is you just simply ask everyone in the room.
So this brings up another question...what if literally all four devices threw an interrupt at the same time? I assume at this point, it's just a matter of designating a desired order. So, the video chip always comes first...VIA #1 comes second...etc.
GARTHWILSON wrote:
There's also my 6502 interrupts primer which is more complete. Yep, I've been reading through that again. I've read it before but it's been a while.
Thanks to all of you. I couldn't build this without you!