This is not entirely 6502 related topic but I know this chips is quite popular among people designing own 6502 systems, so maybe I will be able to find some help here.
Some time ago I used TMS9918 in my 6502 computer, basing my design on this schematic to use it with modern single SRAM memory chip instead of couple of old DRAM chips. It works perfectly fine in 6502 computer, so I decided to use the same video controller in my other project - computer based on vintage Polish CPU - MCY7880 (clone of Intel 8080). This time it is mounted on prototype board, with a lot of wired connections. It also works. Well... Kind of...
I am able to initialize and use chip. Bot writing to and reading from VRAM works. But after some time only last line is visible on the screen. I am noe even sure if this is hardware or software issue.

What I was able to determine for now:
1) Full power cycle of the device restores normal operation of the video chip. Entire screen is visible for some time.
2) Pressing reset only allows device to write the screen once, but then everything except the last line disappears, probably when I try to access VRAM memory corresponding to the higher lines.
3) Pressing chips in their sockets or touching wiring connections under board has no effect, so most likely it not some loose connection or faulty wire. Anyway, in that situation power cycle wouldn't be effective every time,
4) I replaced RAM and TMS9918 with other chips. I had no effect.

You can current version of my code on my Github (procedure VDPPUTC).

Our sister forum, anycpu.org, might be a better place for this topic. But I did have a quick look at the SRAM Replacement pdf you linked to, and the passage quoted below may have relevance to your problem. It strikes me that your symptoms might agree with the theory of the row address appearing on the column address latch. What sort of inverters did you use? And can you maybe slow their response slightly? For example, add a small capacitor to ground -- 50 or 100 pF, maybe -- early in that inverter chain and see if it makes a difference.

-- Jeff

"This situation resulted in improper TMS9918 operation on my prototype; quite frequently the row address would appear on the outputs of the column address latch. Clearly what was needed was more delay between falling edge of /CAS and rising edge of COL. I accomplished this by creating COL from /CAS using three inverter stages in series, relying upon the propagation delay of the additional two inverters to ensure the necessary setup time."

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