Yeah, that was my main suspicion also.

I don't have much at all in the 74ACT range yet. But I do have a couple of 74ACT245's. A quick breadboard test (wiring it up purely as a buffer) last night with the oscilloscope showed they seem to by way faster switching between input and output, so I'll have a bit of a play later on and get back to you.

damn, running a 65C02 at 5V >25MHz and that reliably. that's a lot further than i expected it to go.
my 65C02 SBC can only reach 16MHz. i have tried it a 20MHz Oscillator and it just won't budge.
i thought that was just the natural limit of the 65C02 but i guess i was wrong and the real limit were just my lacking PCB designing skills.

Testing overclock-ability of these chips at different voltages seems important as well. (specifically 3.3V)

though to be honest i'm mostly just saying that because i recently ordered some PCBs for a Shield that plugs onto an (3.3V) FPGA Breakout board i made.
the shield has some SRAM, some Flash, a 25MHz Oscillator, a VGA Connector, and a 65C816 on it.
i doubt it will reach 25MHz, mostly due to the still lacking PCB Skills and the Pin Header connecting both boards, but i see what i can reach and report back (if i remember to do so)
or did someone already see what can be done at 3.3V without crazy 4 layer PCBs and such?

in the meantime, what about the duty cycle of the clock? could it be adjusted to either side to allow for even faster stable Clock Speeds?

I wouldn't write off your PCB making skills just yet. Just cracked 35 MHz on this hideous setup. :lol



Still 5V and still running stable as I write this post. Clock is still being fed from a Raspberry Pi Pico, but now being passed through a 74ACT245 (instead of the 74HC04 that I was using previously).


[edited typo for the ACT245, I incorrectly had 275 in there]

Just shy of 38 MHz at 5V! Getting unstable though, barely have to move to make it crash.



Will look at moving the clock buffer IC on to a very small stripboard over the weekend, so I can get the signal as close as I can to the W65C02. At ~40MHz the waveform is looking pretty nasty over that distance.

According to WDC specifications, the optimal duty cycle is 50%. But, as the lyrics of that old song say, "it ain't necessarily so." It would be worthwhile -- although a tad tricky -- if you could arrange for your experiments to vary the duty cycle.

BTW and FWIW, clock timing (including duty cycle) is discussed in my Visual Guide to 65xx CPU Timing.



Just a reminder that your scope will to some extent limit what you're able to view, and things may not be quite as bad as they seem. For example, if we optimistically assume that the 40 MHz waveform is truly a square wave, then the "corners" of the wave will appear rounded, even on a scope whose bandwidth is hundreds of MHz.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

BTW if you're free to put any values in any locations in the memory map, MOS's original bring-up test, which supposedly exercises the internal critical path, is to have the reset vector point to FFFF, place a JMP at FFFF, and have it wrap around and read FFFF from locations 0 and 1. The wrap-around of the PC is (or was) the critical path. By monitoring the address lines you can see if the 6502 stays within that very tight loop.

(It would in fact be interesting to see how this test fails, as you raise the clock speed, as it must inevitably fail.)

See previous discussion at viewtopic.php?p=85232#p85232

BDD - Sorry, typo there! Right you are 74ACT245. Edited the post now but made reference to the typo at the bottom, to save confusion for people newly visiting the page.

And yes, I do indeed have a second CPU that I can try out in the morning.

Dr Jeffyl - Yep! I actually stumbled on your site a month or so ago. I found it very helpful with understanding the clock and timings. Extremely well done!!

Big Ed - I’ll give that a try. I wasn’t aware of that test at all. I do have easy access to entire memory map with this setup.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Nice test BDD. We should be able to do something similar with Beeb816.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

you were right. my SBC is able to run at higher speeds, despite the PCB being suboptimally designed.
I changed the CPLD to insert a single wait state whenver ROM or IO is accessed. (the ROM/Flash has a maximum access time of 70ns, the FT240X has a minimum access time of 50ns)
and now i can insert a 20MHz Oscillator and it works fine.
i also tested 24MHz using my FT240X, since you can set the Programmable IO Ports to output 1/2, 1/4, or 1/8 of the internal 48MHz USB Clock. and it was working too.

overall that was a lot easier than expected. some wait states for the slower components but other than that it was fairly straightforward.

this gives me a lot of hope for my future 3.3V 65C816 Computer. i'll be aiming for something like 16MHz, but i will try 25MHz in case i won the silicon lottery.

good luck with your own overclocking attempts!

Indeed it does, since the Mk2 revision: 512k of RAM, in a necessarily slightly complicated memory map, but with 4 free high banks. As for speed, 16MHz stable and we've seen 19MHz recently.

Edit: we didn't have a Beeb816 thread until now, but here's a fresh one.