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PostPosted: Wed Jul 14, 2021 8:23 pm 
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Starting this as a new thread as recommended, and expanding upon my design plans.

I'm in the process of designing my third SBC. Unlike my previous builds this one will go straight from schematic to PCB; no breadboarding. For this reason, and to avoid death by feature creep like my last SBC, I plan to start with a relatively simple base system. As a secondary goal I am also trying to avoid buying any new parts as much as possible, and instead reusing what I've already got in stock. Since I'm still in the early design phases on this project I want to get some input and advice before I get too far long.

My initial specs look something like this:

    - 65816 CPU, initially 4 MHz, with plans to go faster down the road
    - 1 MB of RAM (2 x AS6C4008-55)
    - Either a flash ROM, or loading bootloader from a microcontroller. Not yet decided.
    - Two 6522 VIAs
    - NXP 28L92 UART
    - PS/2 keyboard port (probably through a separate microcontroller)
    - Two NES-compatible game controller ports
    - Compact Flash, and/or SD card via SPI
    - Four layer board with internal power and ground planes.
    - Glue logic in GALs

Once the system is up and running over serial console I want to implement VGA video. This is something I really want to do myself (it has fascinated me since childhood), so slapping on a ready-made solution such as a VGA terminal emulator is not an option. I also do not want the performance hit of trying to run the video (which will include graphics) through a VIA or SPI. I want something that least maps registers (and ideally all of VRAM) to the CPU address space. Thus, I need an expansion connector that provides access to the CPU busses.

When it comes to the topic of running CPU busses off board I've read through Garth Wilson's entire website, and scoured the first 40 or so pages of the hardware forum. From what I have read on this topic it seems like the answer is always just "don't do it". I am hoping there is some middle ground here besides that answer and "become a full EE".

So let's say I want to add just a single expansion connector (I'd prefer two or three but I'll settle for one). The type of connector does not matter to me; I like card edge for the retro feels, but I'll go with whatever works best. I understand having this is going to have a trade-off in the form of a lower maximum speed, but roughly how badly? Would I cap out at 4 Mhz? 8 MHz? Are there some mitigation strategies I can use, like buffering and/or terminating the expansion bus?

Note that I am willing to make some trade-offs. If I have to cap out at a few MHz in the interest of having a system on which to experiment, then I can live with that. At least then I could settle on a final design I like, and build a future integrated system around it.


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PostPosted: Wed Jul 14, 2021 10:31 pm 
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I'm very interested in this topic too as it almost mirrors my goals in many ways too. I started the opposite way around so I have already made a working VGA board (not the best on the planet, but it's 100% my own creation) and now I'm working at designing the host.

And like you, my takeaway from Garth's (very awesome work) was "don't do it" also, which was a bit dissuading at the time of reading.

But when you are designing two mammoth projects like this (VGA & Computer), rebuilding your entire project really isn't an option. You might do it once or twice, but when things aren't working you'll end up walking away, which no one wants.

When you look at the size of the Amiga 2000 mainboard, it was massive! And had expansion ports galore.

Attachment:
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amiga.jpg [ 754.51 KiB | Viewed 943 times ]


Our projects are miniscule in comparison and would be lucky to be a quarter this size when completed (and probably run at a quarter of the speed too).

I guess when it comes down to it, expansion ports are part of our design decision, they will be in there. :lol: I guess the question is more of a 'what to watch out for' type thing.

From my projects perspective, I am looking at a system board with CPU/RAM etc. One or two input devices like Keyboard/Joystick. Then maybe two expansion slots that expose the address, data, signals, and other 'future use' pins. Expansion slots being for VGA and Sound at a minimum.


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PostPosted: Wed Jul 14, 2021 10:58 pm 
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J64C wrote:
I'm very interested in this topic too as it almost mirrors my goals in many ways too. I started the opposite way around so I have already made a working VGA board (not the best on the planet, but it's 100% my own creation) and now I'm working at designing the host.


I actually have one already working VGA controller that I built for my last project. The funny bit here is that originally that project was going to be like this one, with expansion slots, but I got discouraged about adding them and tried to cram everything into one design. Since it was all on a breadboard it became unreliable and difficult to debug, and I finally just tore it all down. For a while though it was running decently at 6 MHz and had a video display (but no keyboard...)

That controller I developed is called the TIVI (TIny Video Interface). It's implemented in Verilog on a TinyFPGA-BX. However it is limited by the resources available on that board; the ice40 chip it uses only has 18K of dual-port RAM, and board does not have enough exposed I/O pins to allow the CPU direct VRAM access. So, it implements VRAM access via registers ala the TMS9918. It's not a bad design otherwise. It will do 80x25 text with selectable FG/BG colors, plus hardware blink, a hardware cursor, and hardware vertical scroll. It also supports a 320x200 monochrome mode in which each 8x8 pixel block can have its own fg/bg colors, kind of how the VIC-II works in a C64. With the hardware text scrolling the text display was pretty snappy, even with the CPU writing 2 bytes per char through a single byte data register.

There was supposed to be a larger TinyFPGA-EX that may have overcome those limitations, but it seems like it's stuck in a "coming soon" state. So, I ended up buying a ULX3S, which has much beefier ECP5 FPGA. That chip has enough DP-RAM for a huge (by '816 standards) frame buffer, and enough I/O pins to easily allow it to be memory-mapped. The dev board also has an on-board HDMI port so I don't need to build resistor ladder DACs anymore. At one point I had the TIVI code running on it and outputting a test image over HDMI, but without an SBC around which to develop it I've temporarily put it on the back burner.


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PostPosted: Wed Jul 14, 2021 11:07 pm 
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Quote:
When you look at the size of the Amiga 2000 mainboard, it was massive! And had expansion ports galore.

The Amiga 2000 used a 68000 processor running a hair over 7MHz. How long is a bus cycle on that? And is the expansion slot cycle the same? I understand the max speed of that Zorro expansion bus is about 3½MB/s. I'm not particularly challenging, since I don't know, but I suspect it's a lot friendlier than a 14+ MHz 65816, and that 74HC or 74LS logic would probably do, making it a lot easier to make a big board without running into AC performance problems.

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PostPosted: Wed Jul 14, 2021 11:55 pm 
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From my projects perspective, the max I would need is 7.5 MB/s if that's any indication and running a W65C02 at 12.5Mhz. If I can't pull that off, I'm happy to run at half of both those figures (and so on, until it did work - with 1.5MHz being my minimum target).


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PostPosted: Thu Jul 15, 2021 12:23 am 
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Well, I need to eat my words, at least a little...I didn't dig quite as far back into the hardware forum's post history as I thought! I found a nine year old thread on bus amplifiers and termination that answered some of my questions. The post is here: http://forum.6502.org/viewtopic.php?f=4&t=2260

Some takeaways i got from that thread:

1. I should be using 74AC or 74ABT logic. I was already planning to do that part (well 74AHCT for my buffers, because I have them already, but I can always swap them out down the road as speeds ramp up)

2. Keep line lengths short. This one is kinda a no brainer. :) My target size for my board is going to be somewhere in the Mini-ITX (170x170 mm) to Mini-ATX (200x200 mm) range. Assuming the slots are all grouped together and behind their own buffer, the line lengths should be relatively short. Connector choice still TBD but I'm pretty sure I have some PCI connectors around here I got as part of a bag of random electronics from ebay.

3. Possibly add some passive termination to the expansion bus. 220 ohm to Vcc and 330 ohm to ground was the number I saw suggested in the thread above.

With all this in mind my main remaining question for the experts here is: what lines should get buffered? A0-A23 and D0-D7 seem obvious, but I'm not as sure about other bus support signals like my /RD and /WR signals and the Phi2 clock. The clock I'm particularly worried about as I feel like delaying that through a buffer may not be a great idea. For reference my clock will be driven by a 74AC74 flip-flop, and won't be feeding anything directly other than the CPU, the VIAs, and my glue logic.


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PostPosted: Thu Jul 15, 2021 12:51 am 
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J64C wrote:
From my projects perspective, the max I would need is 7.5 MB/s if that's any indication and running a W65C02 at 12.5Mhz.

Keep in mind that the 65c02 running at 12.5MHz does 12,500,000 memory accesses per second. The 68000 takes three or four cycles per memory access (I don't know which), so at the Amiga 2000's 7MHz speed, it's only dong 1,750,000 or 2,333,333 accesses per second (or actually slightly more, since it's a hair over 7MHz). I really know very little about the 68000, only saying these are things you'll want to take into consideration when comparing its expansion, board size, and construction. Apple intentionally held the 65816-based IIGS's speed down to 2.8MHz because they didn't want it to make the new 68000-based Macintoshes look bad.

Keep in mind that buffers add propagation delay too.

As for terminations, the terminating resistance needs to approximately match the transmission-line impedance to accomplish the purpose. The transmission-line impedance (Zo) depends on the trace width, the separation between it and the ground plane (you have to tell the board house exactly how you want the layers spaced, since otherwise they'll do it however is convenient for them), and the dielectric coefficient between (which is 4.1 for FR4 PCB material). 220Ω to Vcc and 330Ω to ground together make 132Ω. Pulling down to .4V into a 220Ω load makes for (5-.4)V/220Ω=20.9mA per line. Even if everything is strong enough to drive it, that's going to be an awful lot of current if all the lines have this load. (On average, probably only half of them will be low at a time, and the other half, being high, are pulling up against 330Ω which will be a little less current.

I'm all for making goals to carry out your ambitions; I only encourage you to consider everything, to maximize the chance of success.

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PostPosted: Thu Jul 15, 2021 1:24 am 
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Absolutely. And many thanks for pointing all of these caveats out. So much there to consider. And admittedly bus impedances etc, is well over my head right now. With your huge experience, you are able to foresee thing that I couldn't even begin to imagine yet.


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PostPosted: Thu Jul 15, 2021 1:48 am 
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GARTHWILSON wrote:
As for terminations, the terminating resistance needs to approximately match the transmission-line impedance to accomplish the purpose. The transmission-line impedance (Zo) depends on the trace width, the separation between it and the ground plane (you have to tell the board house exactly how you want the layers spaced, since otherwise they'll do it however is convenient for them), and the dielectric coefficient between (which is 4.1 for FR4 PCB material).


The tricky part here of course is that hobby level board manufacturer generally won't have that level of control, since your project is sharing panels with other folks. So unfortunately I think it's going to be some trial and error. With that in mind I think my best best is to try to minimize those trace lengths, in particular keeping the trace delay under the rise time of mysignals. Quoting you from 2012:

GARTHWILSON wrote:
The trace delay time is approximately the trace length (including going through well behaved connectors) divided by the speed of light, divided by approximately .65 since the phase propagation velocity of a transmission line in the FR-4 PCB material is approximately .65 times the speed of light. I don't remember the exact number, but I know that's close. So if a trace were 20cm long, you would have

.2m / 300Mm/s / .65 = 1ns (approximately)

In my NSC data book for 74ABT, it looks like the rise (and fall) time is typically 2ns, but the minimum prop delay (which includes the rise time) is sometimes only 0.8ns, meaning you would be terminating lines down to about 15cm total length. But! Remember he said many take the more conservative approach of terminating if it's more than 1/4 or even 1/6 of that length, meaning that yes, they would terminate 20cm even with LS or HC, and terminate a line as little as 3cm long if it's fed with ABT.


Assuming I used ABT buffers here, and that I go with the most liberal termination guidelines, it sounds like if I keep my expansion bus lengths under 15cm or so I will have decent luck, even without termination. I should be able to fit 2-3 slots in well under that, leaving a bit of wiggle room for trace lengths on actual cards, which I will keep to an absolute minimum as well. If things are flakey I can swap down to parts with slower rise times and just limit my board's maximum speed. As i said in my opening post, I'm willing to make that sacrifice if the result is a working board against which I can develop my video controller

GARTHWILSON wrote:
I'm all for making goals to carry out your ambitions; I only encourage you to consider everything, to maximize the chance of success.


I understand, and I most appreciate the help! I currently feel like I'm stuck between a rock and a hard place. I can't do complete development on my video solution without a CPU to try talking to it, so I need something to use as a development platform. My previous attempt did this by building the whole thing out on a breadboard, but it's so unreliable I'd rather not go down that road again...plus the ULX3S is not at all breadboard friendly due to it's 2x40 expansion headers.


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PostPosted: Thu Jul 15, 2021 2:31 am 
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In the last 3 years I've built a number retro single board computers without address/data/control buffers that either plug into a small (5 slots) RC2014 backplane and interface to various I/O boards over the backplane or have 3-4 expansion slots on the baseboard. The SBC are based on 68K, Z80, Z280, 6502 processors and every pc board design are 2-layer pcb. The key is making the SBC small, from 50mmX100mm SBC that plugs into a backplane to 100mmX100mm baseboard that has 3-4 expansion slots. When a design is physically small and driving few components, it can be fast, even overclocked 50% (or more) over rated frequency. Termination, transmission line effects are not an issue when the physical board is small.

Make it small (100mmX100mm or less) and most signal integrity problems will go away; in addition, the pc boards are dirt cheap.
Bill


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PostPosted: Thu Jul 15, 2021 3:12 am 
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plasmo wrote:
Make it small (100mmX100mm or less) and most signal integrity problems will go away; in addition, the pc boards are dirt cheap.


Yeah 100x100 seems to the cutoff for the super cheap boards. My first SBC was that size, so I use that as a mental reference. I'm not sure I can really fit it all of this in that size unless I do go to a backplane approach, which is an option but I am hoping to avoid it. The sizes I mentioned (170x170 or 200x200) seem more realistic IMHO, and if I keep the expansion slots on their own bus in one corner of the board it should have roughly the same effect.

Although not a strict requirement, sticking to the mini-ITX or mini-ATX form factors would be nice as it would let me use off-the-shelf cases. But again I'm not glued to that, and I can always design and 3-D print something. That would actually be cooler if I was gonna have a built-in keyboard, but speaking PS/2 seems like the less painful route to a keyboard since they are ubiquitous, and talking to them isn't that hard. My design will actually offload that to an AVR; I already have code written for that from the previous project.


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PostPosted: Thu Jul 15, 2021 4:42 am 
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GARTHWILSON wrote:
The Amiga 2000 used a 68000 processor running a hair over 7MHz. How long is a bus cycle on that? And is the expansion slot cycle the same? I understand the max speed of that Zorro expansion bus is about 3½MB/s. I'm not particularly challenging, since I don't know, but I suspect it's a lot friendlier than a 14+ MHz 65816, and that 74HC or 74LS logic would probably do, making it a lot easier to make a big board without running into AC performance problems.

Also, a bunch of buffers/line drivers were used to deal with the bus loading issue. I too recall that the Zorro expansion bus wasn't all that fast—the ISA bus in an IBM PC was faster.

As the Amiga's design progressed with ever-faster 68Ks the discrete logic was replaced with programmable logic to do something about the prop delay through all those gates. I think trying to keep up with the rapid advances in computer hardware that occurred in the latter 1980s was too costly for Commodore to maintain and indirectly led to the company's bankruptcy and liquidation in 1994.

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PostPosted: Thu Jul 15, 2021 5:35 am 
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jmthompson wrote:
I'm in the process of designing my third SBC. Unlike my previous builds this one will go straight from schematic to PCB; no breadboarding. For this reason, and to avoid death by feature creep like my last SBC...

...says he as he puts together a creeping featurism shopping list. :D

Quote:
    - 65816 CPU, initially 4 MHz, with plans to go faster down the road
    - 1 MB of RAM (2 x AS6C4008-55)
    - Either a flash ROM, or loading bootloader from a microcontroller. Not yet decided.
    - Two 6522 VIAs
    - NXP 28L92 UART
    - PS/2 keyboard port (probably through a separate microcontroller)
    - Two NES-compatible game controller ports
    - Compact Flash, and/or SD card via SPI
    - Four layer board with internal power and ground planes.
    - Glue logic in GALs

I don't want to be a Doubting Dan, but I think your proposed system is too complex for a first try. Also, I'd be using a CPLD instead of multiple GALs. Without launching into too much detail, using multiple GALs can create logic race conditions in some cases. I can guarantee that you will be tearing out your hair trying to unravel such a mess.

Quote:
Once the system is up and running over serial console I want to implement VGA video.

You need to consider the work that is involved in generating a raster and putting text (let alone graphics) on a screen. Producing a stable picture with VGA requires jitter-free timing that you may not be able to achieve no matter how fast you run the 65C816. This is why so many hobbyists use some sort of microcontroller or video display controller to produce VGA.

When you get to that point, consider arranging for your video card to be an add-on device working through the expansion bus (next section) you are going to design. :D You feed information to the card, and its processor (whatever that might be) does the grunt work of producing a picture.

Quote:
Thus, I need an expansion connector that provides access to the CPU busses (sic).

No, you don't need an expansion connector with access to the MPU buses. You need an expansion bus that provides the needed signals to support plug-in cards. As Garth advises, do not run the MPU buses off-board. This is no different than what is going on in a PC. Excepting the short-lived VESA local bus that was present in 80486 systems (and not all of them), all buses in PCs are not extensions of the MPU buses. In fact, the modern PCI and PCI-Express (PCI-E) buses run at a speed that is a submultiple of the processor bus speed.

Drive your expansion bus through a 65C22 (S-version, not the N-version). You've got 16-bit bi-directional I/O in the 65C22, handshaking, interrupt capability and a timer, which is everything needed to set up an expansion bus. Plus the 65C22S has strong, low-impedance outputs meant to be interfaced to the outside world.

In concert with the 65C22, simple logic (in your CPLD) and a suitable buffer can produce the /RD and /WD signals required by Intel bus-compatible hardware plugged into your expansion bus. You could even use a second 65C22 as a dedicated interrupt arbiter for your bus—65C22s are relatively cheap for what they can do. So why not take advantage of them?

Once you've worked out the bus protocol, you can connect almost anything without having to worry about the effects of loading down the MPU buses and the inevitable timing snarls that can result. All you will need is a driver for the plug-in card. My guess is a 65C22S could drive three or four cards with no difficulty.

Quote:
When it comes to the topic of running CPU busses(sic) off board I've read through Garth Wilson's entire website, and scoured the first 40 or so pages of the hardware forum. From what I have read on this topic it seems like the answer is always just "don't do it". I am hoping there is some middle ground here besides that answer and "become a full EE".

See above. :D

Quote:
The type of connector does not matter to me; I like card edge for the retro feels, but I'll go with whatever works best.

Card-edge is current technology in all PCs. The PCI-Express bus uses card-edge connectors and runs at 100 MHz. PCI runs at 33 MHz. PCI-X (64 bit PCI, common on server motherboards) runs at up to 133 MHz. My next POC unit is going to use a card-edge connector for expansion—it will be a 0.100" spacing type, which was used in all PCs with ISA buses. We'll see how well that works when I get it built.

Quote:
I understand having this is going to have a trade-off in the form of a lower maximum speed, but roughly how badly? Would I cap out at 4 Mhz? 8 MHz? Are there some mitigation strategies I can use, like buffering and/or terminating the expansion bus?

See above again. :D

Quote:
Note that I am willing to make some trade-offs. If I have to cap out at a few MHz in the interest of having a system on which to experiment, then I can live with that. At least then I could settle on a final design I like, and build a future integrated system around it.

Again, par down your feature list so you can build a first unit with high likelihood of success. Once you get that first unit up and running, study its operation (here is where a good scope and possibly a 16- or 32-channel logic analyzer can be of help) and observe how your timing has worked out. Information gleaned from such observation will assist you in designing and building the next unit that has more features and complexity.

As I've often said, learn how to fly a Piper Cub before you climb into the cockpit of a 747.

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PostPosted: Thu Jul 15, 2021 7:50 am 
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jmthompson wrote:
Once the system is up and running over serial console I want to implement VGA video. This is something I really want to do myself (it has fascinated me since childhood), so slapping on a ready-made solution such as a VGA terminal emulator is not an option. I also do not want the performance hit of trying to run the video (which will include graphics) through a VIA or SPI. I want something that least maps registers (and ideally all of VRAM) to the CPU address space. Thus, I need an expansion connector that provides access to the CPU busses.


As well as Ben Eaters "Worst VGA" thing, I've been following George Foot on YouTube - has some really promising stuff including hardware sprites on a 6502 system (on breadboards). Here is a link to his latest:

https://www.youtube.com/watch?v=A9b6BdymlyE

Might give you some food for thought...

Cheers,

-Gordon

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PostPosted: Thu Jul 15, 2021 12:06 pm 
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jmthompson wrote:
...I didn't dig quite as far back into the hardware forum's post history as I thought! I found a nine year old thread on bus amplifiers and termination that answered some of my questions.

Many thanks for digging so deep and unearthing something useful! Things haven't changed so much - advice and wisdom from the earliest days of this forum may still be relevant, and useful.


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