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PostPosted: Thu Jul 08, 2021 5:43 am 
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Main threads:
6509 dissection
8501 dissection

Side quest:
This thread is a comparison of the 6509 and 8501 clock generator, brought to you by Frank Wolf and ttlworks.

Because the official MOS 6509 datasheet contains an error (PHI1 and PHI2 inputs swapped),
I felt a need to take a closer look at the 6509 clock generator.

;---

Results for the 6509 in short form:

Pin 40 is PHI1_in.
Pin 38 is PHI2_in.

Both pins drive the circuitry inside the 6509 directly/unbuffered.
Each pin has an ESD protection FET.

TTL circuitry for driving the PHI1_in and PHI2_pin of the 6509 can be found in the P500 PET-II schematics.


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PostPosted: Thu Jul 08, 2021 5:46 am 
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Eagle 6.4 schematics for my schematic pictures in this thread,
just in case if somebody needs them.

Note: KiCad is supposed to be able to import these schematics,
unfortunately it doesn't seem to be possible to disable the layers 'name' and 'value' in KiCad schematics,
so making my schematics look nice and clean in KiCad will require some work, sorry.

Attachment:
6509_8501_clock_dissect_schematics.zip [63.29 KiB]
Downloaded 44 times


Last edited by ttlworks on Thu Jul 22, 2021 2:36 pm, edited 1 time in total.

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PostPosted: Thu Jul 08, 2021 5:49 am 
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The silicon of the clock generator in the original 6502 looks completely different
from what we have in the 6509 and 8501.

Since the 6509 was manufactured in an older process technology than the 8501,
it's an interesting question if the first revision of the 6509 did "rocket testing"
for the clock generators of the later MOS CPUs.


When comparing the silicon of the 8501 and 6509 clock generator in one picture,
it appears that some of the parts in the chip layout look quite similar for both chips.

Attachment:
si_8501_6509_clock.png
si_8501_6509_clock.png [ 254.89 KiB | Viewed 899 times ]


In the 6509, the clock generator circuitry is only dead weight:
Some vias are placed differently than in the 8501.
Quite some vias that connect to VCC are missing.
Outputs of all of the driver transistors are not connected to anything.
In the PHI2 driver, gate of the FETs (not) switching PHI2 to GND and gate of the FET (not) switching PHI2 to VCC are tied together.

Attachment:
8501_6509_clock_generator.png
8501_6509_clock_generator.png [ 90.21 KiB | Viewed 899 times ]


Last edited by ttlworks on Fri Jul 09, 2021 5:20 am, edited 1 time in total.

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PostPosted: Thu Jul 08, 2021 5:50 am 
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8501 clock generator:

Attachment:
8501_clock_generator.png
8501_clock_generator.png [ 311.99 KiB | Viewed 899 times ]


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PostPosted: Thu Jul 08, 2021 5:50 am 
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6509 clock generator:

Attachment:
6509_clock_generator.png
6509_clock_generator.png [ 90.1 KiB | Viewed 899 times ]


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PostPosted: Thu Jul 08, 2021 5:51 am 
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That's all for now.

Now back to dissecting the 6530 clock generator...


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PostPosted: Thu Jul 08, 2021 8:17 am 
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Posts: 91
Once again I have to admit that your speed and precision is astonishing!

Great (ttl)works as always.


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PostPosted: Thu Jul 08, 2021 11:38 am 
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Thanks for the kind words. :)


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