Hi Everyone, i haven't been very active for some time due to RL stuff.
but i have still been slowly working on things.

last time i made a 65C02 from scratch in a Logic Simulator called Logisim, to better understand the hardware and potentially improve it.
but people pointed out that a lot of the improvements i wanted to add where already a thing in the 65816 and 65CE02... so that kinda killed that whole thing.

now i'm trying to do the same thing, but use the 65CE02 as the Base to improve upon.
I won't go into detail about what i want to add here, since i want to finish the whole CPU first before making a detailed thread about it.

my problem right now is that there are some things about the CPU that i have problems finding detailed information about...

for example, the ASW and ROW instructions.
in the Datasheet and on Wikipedia, ASW stands for "Arithmetic Shift left Word" while ROW stands for "ROtate left Word".
but there are other sites like commodore.ca and zimmers.net that say that ROW is "ROtate right Word".

so which one is correct? i would personally trust the offical Datasheet and Wikipedia more. but you can never be sure, and it doesn't hurt to ask.
(commodore.ca also seems to get the Addressing Mode (or AM) of INW and DEW wrong, it shows them as using the Absolute AM, but in the Datasheet they use the Base Page AM)

another thing that confuses me is the (D, SP), Y or "Stack Vector Indirect Indexed" AM.
more specifically does it behave differently depending on the mode that the SP is in?

for example, "LDA (0, SP), Y" (with Y = 0x00, SPH = 0x01, and SPL = 0xFF), loads the 2 bytes from 0x01FF and 0x01FF + 1.
with the 8 bit SP i would imagine that this would confine the data being loaded to the Page specified by SPH. so the 2 bytes are loaded from 0x01FF and 0x0100.
but with the 16 bit SP there is no reason to confine the AM to the current Page, as the Stack itself isn't either. so it would load the 2 bytes from 0x01FF and 0x0200.
Also i'm assuming that D is sign extended for the 16 bit SP, so that it reach both forwards and backwards from the SP. it doesn't matter for the 8 bit SP as it wraps around the Page anyways.

other than that i should be able to get the rest of the features working without issues. though if i still got any issues or questions i'll just ask them here in this thread.

Proxy, I can offer you some thoughts, but most of them are only my own inferences.

No opinion on this, I'm afraid. Indeed, the mystery only deepens when we notice that ASW ($CB) and ROW ($EB) seem to have different address modes. The datasheet's opcode matrix shows byte- and cycle-counts that tend to indicate Absolute and Base-Page, respectively.

Again based on the opcode matrix, INW ($E3) and DEW ($C3) show byte- and cycle-counts that tend to indicate Base-Page address mode. This matches the text, so the datasheet is at least self-consistent, which perhaps boosts its credibility.

Yes, 0x01FF and 0x0100 is what I would expect, too. They probably did whatever was easiest -- and that would be to let things wrap within the page.

Doubtful, IMO. That's because the region "under" the stack pointer is unusable due to the risk of getting trashed by interrupt activity. So, I expect that D is zero extended, not sign extended.

Hope this helps! I have a 65CE02, but I'm not set up for running experiments ATM.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Just to note that Pavel Zima has been reverse engineering this chip, so might already have some answers.
Notes on reverse-engineering the 65ce02

You could always ask the designer of the 4502/4510:

https://www.linkedin.com/in/victor-f-andrade-814822b/

He probably doesn't remember, but you never know

Per the 4502 documentation another route to determine for sure would be to track down one of the cross assemblers and documentation and see what the instruction is documented as:



Of course the hardest, but most definitive route would be to source an Amiga 2322 serial card, pop the 4502 out, breadboard it and try the instruction out yourself.

The Datasheet for the C65 was more helpful than the actual CPU Datasheet, thanks for that BigEd!

Rotate Left Word seems to be right as even the C65 Datasheet says it. still weird that there are only Left Rotate/Shift instructions for words, do they just have more uses than Right Shifts/Rotates?

anyways, looking at both the 65CE02 and C65 Datasheets i see what you mean Dr Jefyll, the bytes for ROW don't match up with ASW even though they are supposed to use the same addressing mode. but what is especially confusing is that it's consistent throughout both documents. hmm not sure what to make of that.

the C65 Datasheet also mentions some stuff about the Stack Indexed AM, like Dr Jefyll suspected the "D" Value is not signed extended, though it says that the value is added to "the Stack Pointer (Word)" implying that even in the 8 bit SP Mode it would cross page boundaries? that just doesn't seem correct to me.
for now i'm going to leave it like i have it right now, it crosses the page when in 16 bit Mode, and otherwise wraps around.

and rpiguy2, if i had a 4502 i would probably just put it in a frame and hang it on my wall and not potentially damage it by trying to use it.

also i downloaded the C65 datasheet and made the text selectable, for potential future use. currently i only have it on my DropBox, but someone could upload it to archive.6502.org like done with the 65CE02 Datasheet.
https://www.dropbox.com/s/ptdnigg8548tmwr/C65%20System%20Specifications%20Preliminary%201991.pdf

Small correction but make sure you search for 2232 not 2322 if you're like me and have an eBay search set for it They come up for sale now and then, though I've never been brave enough to take apart working retro hardware just for the chip. It would be cool if there were a non destructive way to play with one...

One thing you may already know is that SBC in decimal mode is supposedly bugged.

Yes sorry it is 2232! I had the opportunity to pick one up years ago at a VCF show and passed on it and now I regret it. It was a later revision with a PLCC 4502 rather than DIP.

For what it's worth, the site seems to be in a Git repo on GitHub, so anybody with an account there should be able to add it to the repo and send a PR: https://github.com/6502org/6502.org

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Curt J. Sampson - github.com/0cjs

(Note: I've just found some notes I'd made back in 2014, which for some reason I didn't post... this seems as good a thread as any. Please excuse that the content doesn't exactly follow on from the conversation here, but I think it's strongly related.)

I found a 1991 document ("System Specification for C65") describing a 4502 CPU core which might be the same one seen as the 65CE02 MPU. Is that the case?

The interesting thing about this 4502 is that it had an extension mode where the stack pointer is 16 bits. I hadn't seen that statement made about the 65CE02 - but now I see that's in the datasheet! (It also has PHZ/PLZ opcodes for the Z register.)







From the C65 doc:


From Michael's doc, and for interest:


(There are some physical 65CE02s around, but I believe it was never sold as a component. It can be found in the Amiga 2232 serial card)

References:
65CE02 datasheet (preliminary) from 1988
65CE02 opcodes by Graham of oxyron, 2009
Commodore Semiconductor Group CSG65CE02 Technical Reference by Michael Steil


System Specification for C65 by Fred Bowen, 1991
(Also found in a flat file here.)

Via two contemporary threads on the LLVMdev mailing list where Edwin Amsler is embarking on a 6502 target:
http://lists.cs.uiuc.edu/pipermail/llvm ... html#74472
http://lists.cs.uiuc.edu/pipermail/llvm ... html#74523
(LLVM being a modern open-source framework for C compilers, among other things.)

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

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x86?  We ain't got no x86.  We don't NEED no stinking x86!