REPLACING THE 65C51—————
Please read this before posting in this topic.
The goal of this topic is to present the technical information needed to replace a 65C51 UART with a non-65xx part, specifically, the NXP 28L91 single-channel UART and the 28L92 DUART (dual-channel UART). I want this topic to be a useful resource for anyone who is building a 65C02 or 65C816 homebrew machine and wishes to include reliable, high-performance TIA-232 serial communication in the design. Off-topic posts will make it harder for a reader to find out what he or she wants to know and may discourage him or her from continuing. So, PLEASE, avoid off-topic discussion.
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2019/12/02"Driving the NXP SC28L91 UART" is available for download. This article discusses programming the 28L91. The paper is not finished and likely has errors—both technical and spelling—in it, but has most of what you need to know to drive the 28L91 in your 65C02 or 65C816 system. Presumably, you have already perused the "Interfacing..." series of articles (below).
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2017/07/10"Interfacing the NXP SC28L92 DUART" is available for download. This article discusses the adaptation of the NXP 28L92 dual channel UART to a 65C02 or 65C816 system, and includes circuit examples.
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2017/06/30"Interfacing the NXP SC28L91 UART" is available for download. This article discusses the adaptation of the NXP 28L91 single-channel UART to a 65C02 or 65C816 system, and includes circuit examples.
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In this forum post, it is mentioned that Western Design Center (WDC) recently issued a revised
W65C51N UART data sheet, in which there is a caveat about the
"stuck TXD empty bit" hardware errata. This bug was first described by
floobydust in June 2013, and once the nature of the bug was fully understood, it was reported to WDC. WDC cooperated in determining what was going on and it was thought at the time that a fix would soon be devised and new parts would soon be available. Nothing of the sort has happened. Given the time that has elapsed since floobydust's report, it can be concluded WDC has decided to not do anything about the bug, viz.:
Quote:
Transmitter Data Register Empty (Bit 4)
The Transmitter Data Register Empty (TDRE) bit is always a 1 because the TSR is loaded when the TDR is written to. TDRE bit cannot be polled to determine when to write the next byte to the TDR/TSR. A delay loop should be used to gate the writing to the TDR/TSR. Transmitter Interrupts should never be enabled.
The above is on page 10 of the latest data sheet.
Succinctly stated, this bug makes it impossible for the 65C51 to indicate when the transmitter can accept a new datum and hence prevents the use of interrupt-driven code to run the transmit side of the UART. Only polled I/O can be used and it too has been compromised by this bug. The programmer must introduce a delay after writing to the transmitter so as to avoid writing another datum before the present one has been fully shifted out onto the wire. Writing too soon will likely result in corruption of the datum being shifted out. Obviously, delaying the MPU after each write results in system throughput degradation during data transmission.
Aside from the hardware errata, the 65C51 represents the state of UART design of the mid-1970s. The 65C51 has a poorly-designed programming model, e.g., one cannot decouple the state of the
CTS input from the transmitter operation, even when XON/XOFF flow control is being exclusively used, and lacks the programming flexibility and performance features available with modern UARTs. About all the 65C51 offers to the modern designer is ease of attachment to a 65xx system.
Given that the WDC 65C51 is the only 65xx family UART currently available that can be operated at the elevated clock rates supported by the current WDC microprocessors, the 65xx hardware designer who needs a UART has a real problem on his hands. There is only one solution, and that is to design out the 65C51 and design in a modern UART.
A number of modern UARTs are adaptable to the 65xx buses without too much effort. The two that I would consider most adaptable are the 16C550, which is produced by a number of vendors, and the SC28L9x series, which is produced by NXP. Both have 16-deep FIFOs, support for a wide range of data rates and flexible programming models. In the past, I have worked with both the 16C550 and various NXP (then Phillips) UARTs and over time, have concluded that the NXP parts are less onerous to work with than the 16C550.
Since we are discussing a single channel UART, the NXP 28L91 would be the equivalent to the 16C550. In many respects, the two devices are equivalent in performance. However, the 28L91 was designed to work with both Intel and Motorola buses, which gives it more hardware flexibility. Also, the 28L91 has a precision counter/timer that can be used for a wide variety of functions, such as generating a "jiffy" interrupt for timekeeping and/or task switching purposes, as well as generating non-standard data rates.
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The 16C550 is, it would seem, the only modern UART readily available in a DIP package, which is, of course, very hobby-friendly. The 28L91 is available in QFP44, which is not hobby-friendly, and has also been produced in PLCC44, for which sockets with 100×100 mil pin layouts are readily available (including wire-wrap versions), making PLCC44 practical on perf board. The NXP part number for this device is
SC28L91A1A, which as noted above, is not available through regular parts sources. Since, as of this writing, it is available through wholesale parts liquidators, I am proposing that the PLCC44 version of the 29L91 be the "new 65C51."
NOTE: As the NXP 28L92 dual-channel UART (DUART) has the same interface and physical footprint as the PLCC44 form of the 28L91, the former is recommended for new builds.
Obviously, the 28L91 is not a "bolt in" 65C51 replacement. However, the required glue logic is easy to implement with discrete gates or a PLD, and timing is not a problem—the 28L91 will easily handle a system running at 10+ MHz without wait-states (my POC V1.2 unit is running at 20 MHz with a 28L92 and one wait-state on I/O accesses). When configured in Intel mode, separate
/RD (read data) and
/WD (write data) signals must be derived from the MPU's
RWB output. As many 65xx designs use SRAM with similar control inputs, these signals may already be present. The 28L91's time base, referred to as the "X1 clock," is normally 3.6864 MHz, and may be generated with a crystal circuit or a can oscillator, the latter strongly recommended. I am working on generalized schematics that illustrate how to adapt the 28L91 to a 65C02 or 65C816 system with a minimum of logic.
Driving the 28L91 is somewhat more involved than driving the 65C51, as there is more to configure during initial setup, as well as more in the way of status and control functions. Plus the presence of the receiver and transmitter FIFOs tends to demand a different programming approach than that used with the 65C51. However, it's not complicated. I am in the process of preparing a paper on programming theory, complete with code examples that will be adaptable to the 65C02 and 65C816 (use of the 28L91 with an NMOS MPU is not recommended).
Let me know your thoughts. I'm hoping everyone who needs serial communication in their project finds this topic useful.