Regarding very large SRAM arrays for '816, here are some ideas I was doodling with a few years back. Details could vary, but I'll explain the principles I had in mind.
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I consider speed a priority, and there are 32 half-megabyte RAM chips. We
could drive the 32 chip selects from the outputs of four '138 decoders, then put another decoder upstream to select one of the four, but that'd be unacceptably slow. Instead, I relied heavily on the 1G series of single gates (which I talk more about
here). The defining feature of these little guys is their
speed -- the
maximum prop delays are only about 3 ns.
I used two address latches to capture the Bank Address, one that inverts and one that doesn't. Thus, without resorting to putting inverters in the path, we have both active-low and active-high versions of A23-A16 available. And a three-input 1G gate can use the true and inverted address lines to pick out a space that's one-eighth of the total amount... all in just a few ns !
One-eighth is still too coarse, and it means there'll always be a
row of four chips which all get a Chip Select at once. But you'll notice WE and OE are directed only to the appropriate
column of IC's. There'll still be some power wasted by the three IC's which are selected but not accessed. It's a tradeoff of this particular implementation of the row/column approach... but OTOH it's the row/column approach which lets us avoid a "slow as molasses" cascade of 138's.
The address inputs of all 32 RAM's are connected in parallel, which unfortunately adds up to a substantial capacitive load. I don't know of a good remedy for that, but I
have shown an alternative to having the
data IO pins of all 32 RAM's connected in parallel.
It's optional. The decision to split the bus and include two '245 transceivers (as shown) isn't baked in -- you could use 1, 2 or 4 transceivers. By splitting the bus and using 2 or 4 you increase the chip count somewhat but you reduce by 1/2 or 3/4 the bus capacitance that needs to be charged and discharged each cycle. Reduced capacitance improves speed and reduces power consumption and the effects of ground bounce in the system. (Speaking of ground bounce: with a large memory array you REALLY don't wanna use an '816 that's in DIP. Choose an alternative package -- one that has multiple ground and power pins.)
Then there's the matter of decoding IO addresses (see diagram below). Once again I've used the tiny, 3-input gates, as they can triple the input capability of a '138 or '521 and there's minimal added delay (3 ns). As drawn, the logic wants all of its inputs to be zero, but you can easily customize to detect other addresses.
You'll notice in the diagram above that the IO-SPACE\ signal doesn't prevent Chip Select from reaching the RAM chips. Instead it merely prevents OE from being issued, and that means the decoder timing margin is favorable (because in any case OE won't try to go true until PHI2 rises).
I've made no provision for ROM access. That's partly because I ran out of time, but also because I think it's better to use a Blind Loader or similar scheme which simply initializes RAM at powerup and before the full clock rate is applied. I'll add some links to loaders later.
Regarding the splitting the bus and using more than one '245: probably you'll connect your IO devices to one of the two (or four) sub-buses. The alternative is to connect the IO to its own '245 attaching to AD7-AD0. (Or connect the IO directly to AD7-AD0, but the '245 approach is more forgiving.)
Something else I overlooked re multiple 245's is the concern that a RAM data bus could float to invalid levels (thus increasing power consumption) if left un-accessed for too long. Maybe I worry too much.
But as a solution you could either install bus-hold devices or re-jig things so it's A0 (not A23) which selects between the buses. Then then you'd be almost certain that neither could remain un-accessed for too long.
BTW, when mixing modern TTL-output-level RAM's with WDC CPU's always remember to use a"T" variant (such as 74ACT) for your 245's.
-- Jeff
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here but it's been done - although I only vertically stacked 2 myself...