TTL Compatible... NOT! ( modern WDC CPU's )

In this thread I'd like to talk about the practice of using modern WDC CPU's in conjunction with RAM's, ROM's or PLD's etc whose output specifications only guarantee TTL voltage levels. Can the inputs of WDC processors be reliably driven by TTL voltage levels, or is it better to include pullups or level shifters? Are WDC's inputs "TTL compatible"?

We will see they are not. It's true that some RAM's, ROM's and PLD's have a limited degree of WDC compatibility in the sense that they exceed TTL specs. But WDC's inputs are not TTL compatible. WDC inputs are markedly different from Rockwell's, for example. A comparison of Rockwell and WDC input specs reveals this, and the info is confirmed by my actual testing, reported below. Rockwell CPU's can reliably be driven by TTL voltage levels, but WDC chips are TTL Compatible only in the anecdotal sense. People have reported success using them in a TTL setting -- it's not uncommon. But this is not a robust combination, nor one that's even guaranteed to work.

Datasheets specifications can be hard to interpret, so I've prepared two sets of graphics. The first set is slightly OT because it discusses gates, not CPUs. But that's a good analogy, because most of us already know it's an iffy proposition to have TTL outputs driving CMOS inputs such as those of the 74HC series. (The situation with gates is well known, and my graphics are based on a diagram excerpted from page 4 of the attached document from Texas Instruments.)

This doesn't mean a 74HC device is guaranteed to fail.... but if it works it'll be for reasons that can't be relied upon:

• The output may come from a chip whose highs are higher than spec and whose lows are lower than spec. And,
• on the input side, you'll notice that the specs call for highs that are above the actual transition point and lows that are below that transition point. So, the specs call for some extra margin. But cutting corners with that margin won't necessarily result in failure.

What I hope will jump out at you is the fact that a TTL high which merely satisfies spec (ie, doesn't exceed spec) will fail to drive a 74HC input high, because the transition point won't be achieved. It is actually imperative for the TTL chip to exceed the VOH spec. Indeed, you'll even want it to exceed the transition point somewhat; that's so you'll have a little bit of noise immunity (imperative to avoid flaky operation).


Here's the other set of graphics, and now it's CPU inputs I'm illustrating. It's much the same story.


My reference for logic family voltage levels is the TI document attached. Unlike datasheets, it mentions the actual transition voltage -- something which datasheets typically omit, for various reasons. (Manufacturers want to reserve themselves some leeway. And the customer supposedly doesn't need to know the transition point anyway; their job is simply to adhere to the max and min specs.)

For 65xx CPUs I found it necessary to do my own research. I measured the data bus input transition voltage for three 65xx CPUs, as follows. (I haven't tested WDC microcontrollers, but I see no reason to expect them to be different.)

Rockwell R65C02P4: 1.47V
WDC 'C02: 2.6V
WDC '816: 2.57V

From this we see that driving a Rockwell CPU is like driving 74HCT series CMOS. And driving a WDC CPU is like driving 74HC series CMOS... which is to say, for reliable operation you'll need pullups or a level converter IC if the driving IC only guarantees TTL levels.

In a subsequent post I'll share the test circuit I cooked up -- I'm rather proud of its simplicity. And I have plans to verify the input transitions for other inputs such as IRQ and BE. But with summer coming on I'm not sure how soon I'll get around to doing that...

-- Jeff

PS: mug shots of the suspects:[b]TTL

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Agreed.

Do you believe that I measured the data bus input transition voltage for three 65xx CPUs? I did.

When I applied 2.4V -- a valid TTL high -- to the WDC chips, they thought it was a zero. To perceive a one, the '816 needed 2.57 volts and the 'C02 needed 2.6.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Thanks for measuring actual parts, Jeff! Beeb816 has just been exploring this territory.

Is the lack of TTL input compatibility really surprising, given the voltage range that the WDC CPUs run at?

Still digesting the real-life significance of these disturbing results.

I don't know much about CMOS design, but I cannot imagine that it takes much more than 'a little narrower here, a little closer there' to bias down the switching point of the input buffer transistors...

Looking at the specs of, say, CMOS-compatible AT28C256, the minimum specified output high voltage is 2.4V. Same for the SRAMs i looked at; it seems to be what 5V operation means.

How is it possible to design a CPU that is not technically compatible with any known memories and peripherals, requiring level translation for reliable operation? And manufacture 'billions' of said CPUs? Over many decades? And also, design a 'new improved' CPU?

Gah. There is no smilie to match this particular mix of dismay and annoyance. This hobby was supposed to be a way to reduce stress and get away from bulls**t. As in, after decades there are no surprises like this in our hardware. WDC does not fail to surprise.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

My take is that WDC haven't done very well here, on the chip front. (I would say they've never made billions of parts - they've licensed their IP many times, but that's a different thing.)

We do see lots of successful projects here, so in practice things are not so bad, at hobbyist scale. But people do sometimes have unreliable behaviour which is difficult to track down, and this is a possible cause.

Now that I think about it, Apples and Commodores have buffered busses.

_________________
In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

The results may not be to our own liking, but WDC's decision to put the transition point around 50% was balanced and reasonable. There's a whole other world out there, where 5V supplies are not the norm. (Martin A, you hinted at this, too.)

Given the customers they serve, WDC apparently decided TTL Compatibility has more downside than upside.

And for us it's no great hardship. Pullup resistors are tiny and cheap. And, as Garth noted, an '816 will usually have a '245 nearby anyway. Just be sure you specify a "T" variant, such as 'HCT245 or 'AHCT245.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

To measure a CPU's input transition point I wanted something simple -- suitable for a solderless breadboard -- and this (below) is the essence of what I came up with.

- when the potentiometer is at its lowest extreme, the CPU reads nothing but $65 on the bus.
- when the potentiometer is at its highest extreme, the CPU reads nothing but $E5 on the bus.

The $65's get interpreted as an endless series of 2-byte $6565 instructions; this is ADC $65 (using z-pg address mode). The $E5's get interpreted almost identically, but now it's SBC $E5 instead of ADC $65. These are both 3-cycle instructions, so the timing never varies. What does vary is the internal operation and the z-pg address that gets fetched on cycle 3. Address line A7 will go high or low according to whether the CPU thought the value from the potentiometer was a 1 or a 0.

As I increased the pot upward from 0 or downward from +5, there was no effect at all until I was within a few mV of the transition point. Then A7 would begin wavering erratically, which didn't surprise me as there was probably a few mV of noise superimposed on the signal arriving at D7. The erratic result ceased once the voltage from the pot was sufficiently above or sufficiently below the transition point.

BTW, most of the voltages in my diagrams are taken from WDC doc or the TI doc I mentioned. Notice I can't verify WDC's or anyone else's VIH Min or VIL Max because these numbers are mere recommendations, the result of judicious and somewhat arbitrary decisions made by the manufacturer. I can't observe or verify VIH or VIL because nothing happens when those points are crossed. All I can observe is the transition points for the samples tested.

I find it encouraging that, for both Rockwell and WDC, the observed transition point sits midway between the published recommendations VIH and VOL. Were it otherwise I would suspect an error somewhere. Instead, I believe the experiment and the published figures support one another. I now have increased confidence in the WDC doc, at least in the limited context of VIL and VIH for the data bus.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I imagine resistors would slow down the transitions. Is there enough slack to accommodate the delay? I have no idea what the capacitance of the bus lines is...

Edit:

My other thought was to operate all non-WDC periphs at 5.3V (or alternatively drop the CPU voltage to 4.6V or whatever)... An extra regulator vs. 24+ resistors...

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

FWIW both my Ruby 6502 and '816 boards have 8 x 10K pull-up resistors on the upper 8 address lines and they work just fine at 16Mhz.

There is no buffer on the '816 data bus just a latch on the data bus to provide A16:23 (Implemented in a GAL). The resistors have nothing to do with signal levels but are for another reason to do with communicating between the 02/816 and the ATmega host cpu. D0:7 and A0:7 are connected to both 6502/816 and the ATmega as well as the SRAM.

I don't have the test kit to tell me that my boards shouldn't work as they seem to work just fine. The signal levels is not something I've considered in the past but it's both interesting (and curious) to read about these potential issues.

-Gordon

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--
Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

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x86?  We ain't got no x86.  We don't NEED no stinking x86!