Dual Core Bank Switching
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Sheep64
- In Memoriam
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- Joined: 11 Aug 2020
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Dual Core Bank Switching
I am working on dual core bank switching. The memory map is intended to approximate Apple, Acorn and W65C265 with equally poor fidelity. A mono core implementation may be of immediate interest to cbmeeks who has been considering variations of Apple memory map.
- Attachments
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- dual-core-bank0-0-1.pdf
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- dual-core-bank0-0-0.odg
- (8.85 KiB) Downloaded 81 times
Re: Dual Core Bank Switching
What exactly do you mean by dual core bank switching? Sorry not clear about the attached diagram.
2 cores in an FPGA running on the same memory?
2 6502s running on the same memory?
What do you mean by bank? Each core/cpu has it's own view of memory, including the classical view of a bank of 64k memory.
Switching memory access between two CPU is classically done using time sharing - one CPU takes one half of the clock cycle, the second CPU uses the second half (one CPU gets the inverted clock of the other, with bus drivers to separate the address bus. The old 6502 does not even need to separate the data bus in that case, as can be seen in the Commodore dual drive floppies that actually use this.)
André
2 cores in an FPGA running on the same memory?
2 6502s running on the same memory?
What do you mean by bank? Each core/cpu has it's own view of memory, including the classical view of a bank of 64k memory.
Switching memory access between two CPU is classically done using time sharing - one CPU takes one half of the clock cycle, the second CPU uses the second half (one CPU gets the inverted clock of the other, with bus drivers to separate the address bus. The old 6502 does not even need to separate the data bus in that case, as can be seen in the Commodore dual drive floppies that actually use this.)
André
Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/