BigDumbDinosaur wrote:
[...] the data bus is TTL-compatible. This is based upon my observations of my POC units, which use ROM and SRAM whose outputs are TTL-level.
Unlike vintage 65xx CPU's such as Rockwell, whose inputs are specifically tailored to receive TTL levels, modern WDC CPU's have inputs which make no accommodation for being driven at TTL levels. A quick comparison of Rockwell and WDC specs confirms this, as do the results of some controlled experiments which I'll write up soon. Edit:
done.
BigDumbDinosaur wrote:
I doubt stable operation would be possible if the 65C816 insisted on having the data bus driven to CMOS levels.
This reasoning would be logical only if we were certain your EPROM and SRAM fulfill the spec for a TTL high
without exceeding it. But in fact it's entirely routine for ROM and SRAM to exceed that spec, and that's what enables the '816 in your POC to function -- it actually
requires the other chips to exceed the TTL spec. And of course that's not guaranteed -- the amount of undocumented leeway may be as small as zero.
Noise immunity is sharply or even fatally reduced, as compared to using a truly TTL compatible '816 (were one available * ). Thus your success depends on luck and circumstances -- much the same theme you yourself invoked in a different context
here:
BigDumbDinosaur wrote:
if it's a production item you need to design for worst-case. If it's a hobby unit, you can design less conservatively, knowing there may be a case where it won't work.
-- Jeff
Edit: * - apparently GTE produced such an animal back in the day. But modern WDC parts are a horse of a different color.
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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html