BigDumbDinosaur on Thu 14 Jan 2021 wrote:
To me the question would be "What's the point?"
I found this to be a very helpful exercise. Of my viable attempts, the doodles look like transistor versions of the Garth Wilson Special NAND gate address decode. For this, I've learned that there might be borderline cases where transistors are more suitable for address decode than a 74x00.
BigEd on Sat 16 Jan 2021 wrote:
ROM (seems to) need active select.
What is the consequence of vectors being absent? If the data bus is pulled high then all vectors load program counter with $FFFF which then executes opcode $FF. This conflates all of the vectors and incurs interrupt latency but it allows ROM select on A15. Unfortunately, this prevents read/write access to page $00 and page $01. Although is may be trivial to move base page and stack on 6502 variants, the conflated vectors make interrupts indistinguishable from reset. This may not be useful in the general case.
I also considered particularly nasty memory maps in which A5, A6, A7 provide differing combinations of ROM select, RAM select and I/O select. Without bus contention, this provides a maximum of 32 bytes ROM, 32 bytes RAM and 32 byte I/O on every page. I presume someone will see that as a programming challenge. However, I could not find a method to get such a system into a stable state.