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Something is missing, although maybe in my own understanding. (I don't have data on the 6541.) I assume it uses some of the same address map for I/O. How does it make sure you don't read from memory for example when it's supposed to read from the built-in peripherals (input ports, timers, status register, etc.)? Will it read from memory anyway but just ignore it so it doesn't cause trouble and buffer it so there's no bus contention?
If that's taken care of, I'll continue.
> To reduce the chip count I'm intending to use a PLD for all the glue logic
You could actually do it with the same number of ICs (or even fewer) without the PLD, keep up to 65,280 bytes of RAM (minus whatever the 6541 uses for I/O), and maybe still have less propagation delay. What I'm thinking of is using a 74ACT521 (or '688-- same thing-- an 8-bit magnatude comparator) to select the top 4K (or 2K or 1K or 512 bytes or 256 bytes) for ROM. I don't have a way to post a diagram, so I'll write kind of a wiring list here. P0-7 are 8 data A inputs, Q0-7 are 8 data B inputs, E\ is the enable input (sometimes used for cascading these), and (P=Q)\ is the output, low if the chip is enabled and the two sides' bits are the same.
On the '521:
P7 to A15
P6 to A14
P5 to A13
P4 to A12
P3 through P0 grounded-- they're extras if you really want 4K for ROM. (You could use them and go all the way down to 256 bytes of ROM.)
Q7 through Q4 connected to +5V.
Q3 through Q0 grounded if you really want 4K ROM.
Ground the E\ input.
The (P=Q)\ output is the ROM select. It is not usually necessary to bring phase 2 into the ROM select, and certainly not necessary to bring R/W\ into it.
Then use a single 128Kx8 SRAM (just grounding one of its address bits so you're only using half of it). I checked my data books on three different ones, and they all had a CS1\ and a CS2. The 74ACT521's (P=Q)\ output also goes to the RAM's CS2, and then you take phase 2 through an inverter to the RAM's CS1\. If the 6541 had a phase-1 output, you could use that instead and skip the inverter. R/W\ goes directly to the RAM's WE\, and you ground the RAM's OE\. Even though the OE\ is grounded, the outputs will only be enabled when you're reading the RAM.
If the inverter above has a Schmitt-trigger input, you can use another section of the same IC for the reset and forgo the Dallas part, although this requires a capacitor and two or three resistors.
I assume you wanted to switch the ROM out so you'd have more RAM. Since the scheme above allows keeping all but one page of RAM, you may not need to switch the ROM out (although it's still easy). That frees up another I/O bit on the 6541. The other reasons to switch ROM out would be because available RAM is faster (but you're only going 4MHz anyway, so I doubt that's an issue), and to be able to write to the vectors at FFFA-FFFF.
Your inverters between the UART function and the line drivers and receivers are very much out of the ordinary. Normally the UART's polarities are such that when the line drivers and receivers invert the signals (as they all do), then it all comes out right.
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