Hi,

I made a dual 6502 SMP system. Bus arbitration is performed by MLB, RDY, and BE. Read-modify-write instructions such as INC are treated as atomic operations. You can implement mutexes by using LSR, for example.

https://github.com/hatsugai/Dual6502

hatsugai

That seems very nice and simple!

It looks like you have a single RAM but run the two CPUs on opposite phases - so presumably they both run at full speed until an MLB from one of them locks the bus for a few cycles?

Photos from your repo (hope that's OK):

Thank you for the comment and images.

Yes, two CPUs run with no wait except the arbitration case. Thanks to the BE signal, no bus buffer is needed. The signals MLB, RDY, and BE make SMP so simple. the design of 6502 signals is great, I think.

memory space (can be configured easily by programming GAL):

0000H - BFFFH separated
C000H - FFFFH shared

There is a room to improvement: For example, the wait time can be reduced by moving the timing of MLB with an extra circuit.

hatsugai

Oh, that's good: some shared and some private memory.